Cadence Platform Accelerates Microchip’s Data Center Solutions SoC Development

Article By : Cadence Design Systems Inc.

The Palladium Z2 provided Microchip with 2X better emulation capacity, enabling more simultaneous users and 1.5X greater performance gains.

Microchip Technology Inc. has deployed Cadence Design Systems Inc.’s  Palladium Z2 Enterprise Emulation Platform for the development of its next generation ASIC products targeting high-performance and scalable SoC solutions for data centers. The Palladium Z2 platform provided Microchip with 2X better emulation capacity, enabling more simultaneous users and 1.5X greater performance gains versus the previous generation emulator while maintaining full compatibility with existing emulation setups and use models.

The Palladium Z2 platform provides an early model of the ASIC for Microchip’s software and firmware development teams, which is essential to meeting their goal of successful first-pass silicon and software integration. Leveraging the congruency of the Palladium and Cadence Protium Enterprise Prototyping databases, Microchip saved several weeks of FPGA prototyping bring-up and hardware and software integration debugging time. In addition to providing the same RTL databases, the Palladium and Protium dynamic duo offers design environments that share the same in-circuit and virtual interfaces, making the debug process completely seamless and transparent to software and hardware engineers.

“At Microchip, we develop highly complex and secure SOC solutions for leading cloud data center providers that require robust verification platforms that can easily handle our multi-chip systems,” said Riad Ben-Mouhoub, senior technical staff engineer at Microchip. “The common compile flow offered by the Palladium and Protium dynamic duo, combined with unified peripherals, allows us to distribute verification workloads freely between the two platforms. With the new Palladium Z2 platform, the 2X higher gate capacity and 1.5X faster runtime performance allowed us to implement our largest multi-chip systems efficiently to meet our challenging time-to-market and quality requirements. Our migration from the Palladium Z1 platform to the Palladium Z2 platform was extremely smooth and only required a recompilation of our current databases.”

The Palladium Z2 Enterprise Emulation Platform and Protium X2 Enterprise Prototyping system are part of the Cadence verification full flow and support the company’s Intelligent System Design strategy. The Cadence verification full flow is comprised of core engines and verification fabric technologies that increase verification throughput and design quality, fulfilling verification requirements for a wide variety of applications and vertical segments.

 

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