Cadence Launches AI-Driven Verification Platform

Article By : Cadence Design Systems Inc.

Cadence's Verisium leverages big data and AI to optimize verification workloads, boost coverage, and accelerate root cause analysis of bugs.

Cadence Design Systems Inc. has launched the Verisium Artificial Intelligence (AI)-Driven Verification Platform, a suite of applications leveraging big data and AI to optimize verification workloads, boost coverage and accelerate root cause analysis of bugs. The Verisium platform is built on the new Cadence Joint Enterprise Data and AI (JedAI) Platform and is natively integrated with the Cadence verification engines.

As SoC complexity continues to rise, verification has become a critical path for system time to market, often consuming significantly more compute and human resources than any other silicon engineering task. The release of the Verisium platform represents a generational shift from single-run, single-engine algorithms in electronic design automation (EDA) to algorithms that leverage big data and AI to optimize multiple runs of multiple engines across an entire SoC design and verification campaign. By deploying the Verisium platform, all verification data, including waveforms, coverage, reports and log files, are brought together in the Cadence JedAI Platform.

Machine learning (ML) models are built and other proprietary metrics are mined from this data to enable a new class of tools that dramatically improve verification productivity. Using the Cadence JedAI Platform, Cadence is able to unify its computational software innovations in data and AI across Verisium AI-driven verification to Cadence Cerebrus Intelligent Chip Explorer’s AI-driven implementation and Optimality Intelligent System Explorer’s AI-driven system analysis.


Redefining Automotive Electronics

Automation across vehicle cockpits, driver assist systems (ADAS), and autonomous driving is critical for new E/E architectures, sensor architectures, and high-bandwidth in-vehicle communications. As part of the new zonal architectures to enable autonomous driving, radar, lidar, and cameras are vital sensors undergoing rapid improvements. A new class of high-performance system-on-chips (SoC) and system-in-packages (SiP) is needed to process all sensor data. Furthermore, the dramatic increase of the electronic content in vehicles drives the trends toward integrating more functionality on a chip, meeting stringent safety, reliability, and security requirements. Autonomous driving platforms targeting maximum performance running at giga-hertz frequencies must be designed and optimized for scalability, power efficiency, thermal, and EMI robustness.

In his presentation “Redefining Automotive Electronics,” Robert Schweiger, Director, Automotive Solutions at Cadence Design Systems Inc. will provide an overview of automotive trends and the implications for SoC and system design for sensors and automated driving platforms.

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The initial suite of apps available in the Verisium platform are as follows:

  • Verisium AutoTriage: Builds ML models that help automate the repetitive task of regression failure triage by predicting and classifying test failures with common root causes.
  • Verisium SemanticDiff: Provides an algorithmic solution to compare multiple source code revisions of an IP or SoC, classify these revisions and rank which updates are most disruptive to the system’s behavior to help pinpoint potential bug hotspots.
  • Verisium WaveMiner: Applies powerful AI engines to analyze waveforms from multiple runs and determine which signals, at which times, are most likely to represent the root cause of a test failure.
  • Verisium PinDown: Integrates with the Cadence JedAI Platform and industry-standard revision control systems to build ML models of source code changes, test reports and log files to predict which source code check-ins are most likely to have introduced failures.
  • Verisium Debug: Delivers a holistic debug solution from IP to SoC and from single-run to multi-run, offering fast and comprehensive interactive and post-process debug flows with waveform, schematic, driver tracing and SmartLog technologies. Verisium Debug is natively integrated with the Cadence JedAI Platform and other Verisium apps to enable AI-driven root cause analysis with the support of simultaneous automatic comparison of passing and failing tests.
  • Verisium Manager: Brings Cadence’s full flow IP and SoC-level verification management solution with verification planning, job scheduling, and multi-engine coverage natively onto the Cadence JedAI Platform and extends it to support AI-driven testsuite optimization to improve compute farm efficiency. Verisium Manager also integrates directly with other Verisium apps, enabling interactive push-button deployment of the complete Verisium platform from a unified browser-based management console.

“AI and big data are transforming the world around us,” said Paul Cunningham, senior vice president and general manager of the System & Verification Group at Cadence. “To realize this transformation in our core EDA business, we must build new technologies that optimize across multiple runs and engines. With the Verisium platform, we enter a new era of AI-driven verification built on the Cadence JedAI Platform. Our journey is just beginning, but users are already seeing dramatic improvements in their verification productivity and efficiency using the Verisium platform.”

The Verisium AI-Driven Verification Platform is part of the Cadence verification full flow, which includes Palladium Z2 emulation, Protium X2 prototyping, Xcelium simulation, the Jasper Formal Verification Platform and the Helium Virtual and Hybrid Studio. The Cadence verification full flow delivers the highest verification throughput of bugs found and root caused per dollar invested per day of project execution. The Verisium platform and verification full flow support the company’s Intelligent System Design strategy, enabling SoC design excellence.

 

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