Cadence Expands VIP Portfolio

Article By : Cadence Design Systems Inc.

Cadence's latest VIP offerings empower customers to confidently develop their next-gen industrial, automotive, hyperscale data center, and mobile SoCs.

Cadence Design Systems Inc. has expanded its Verification IP (VIP) portfolio with the release of 15 new solutions that enable engineers to quickly and effectively verify their designs to meet the specifications for the latest standards protocols. The new Cadence VIP offerings empower customers to confidently develop their next-generation industrial, automotive, hyperscale data center and mobile SoCs while keeping pace with the latest industry standards, including LPDDR5x, MIPI CSI-2 4.0 and UFS 4.0, and the newest versions of the USB4, Arm AMBA 5 CHI and GDDR interfaces.

The new Cadence VIP offer customers a comprehensive verification solution for the most complex protocols. Cadence customers have access to a consistent API across all VIP with complete bus function models (BFMs), integrated protocol checks and coverage models, facilitating rapid adoption.

All Cadence VIP solutions include Cadence TripleCheck technology, which provides users with a specification-compliant verification plan linked to comprehensive coverage models and a test suite to ensure compliance with the interface specification. The new VIP also support the expanded Cadence System-Level Verification IP (System VIP), which provides SoC-level test libraries, performance analysis, and data and cache coherency checkers.

“STMicroelectronics has successfully utilized a broad range of Cadence VIP, including Arm AMBA, Memory Models, MIPI I3C and CSI-2, eUSB2 and the advanced Cadence System VIP solution, which enabled us to deliver industry-leading solutions for key projects, including ST Industrial MCUs and MPUs,” said Philippe d’Audigier, system-on-chip hardware design director at STMicroelectronics. “Cadence continues to deliver new VIP offerings and advanced SoC verification technologies that support the latest standards. We look forward to continuing our collaboration to develop our next-generation products.”

“As requirements evolve and demand increases for higher bandwidth, lower power and more effective cache coherency management, new protocols arrive to address these issues,” said Paul Cunningham, senior vice president and general manager of the System & Verification Group at Cadence. “By introducing these 15 new VIP, Cadence provides customers with solutions that ensure they can keep up with evolving standards. Our customers can confirm their designs comply with the standard specifications and application-specific timing, power and performance metrics, providing the fastest path to IP and SoC verification closure.”

The new VIP solutions are part of the broader Cadence verification full flow, which includes Palladium Z2 emulation, Protium X2 prototyping, Xcelium simulation, the Jasper Formal Verification Platform, the Helium Virtual and Hybrid Studio and the vManager Verification Management Platform. The Cadence verification full flow delivers the highest verification throughput of bugs per dollar invested per day. The VIP solutions and verification full flow support the company’s Intelligent System Design strategy, enabling SoC design excellence.

 

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