Cadence Enables 10x Faster Concurrent Full-chip Optimization and Signoff

Article By : Cadence Design Systems Inc.

The Cadence Certus Closure Solution automates and accelerates the complete design closure cycle from weeks to overnight—from signoff optimization through routing, STA, and extraction.

Cadence Design Systems Inc.’s Certus Closure Solution addresses the growing chip-level design size and complexity challenges by automating and accelerating the complete design closure cycle from weeks to overnight—from signoff optimization through routing, static timing analysis (STA) and extraction. The solution supports the largest chip design projects with unlimited capacity while substantially improving productivity by up to 10x versus current methodologies and flows.

The Cadence Certus Closure Solution eases the design signoff closure bottlenecks and complexities that come with developing today’s emerging applications like hyperscale computing, 5G communications, mobile, automotive and networking. Prior to the introduction of the solution, a full-chip closure flow involved manual, tedious processes from full chip assembly, static timing analysis, and optimization and signoff with 100s of views, taking designers months to converge. The new solution provides a fully automated environment that is massively distributed for superior optimization and signoff. This allows concurrent, full-chip optimization through an engine shared with Cadence’s Innovus Implementation System and the Tempus Timing Signoff Solution, eliminating iterative loops with block owners while enabling designers to make quick optimization and signoff decisions. Furthermore, in conjunction with the Cadence Cerebrus Intelligent Chip Explorer, designers can experience additional productivity improvements from block-level to full-chip signoff closure.

The Cadence Certus Closure Solution provides customers with innovative scalable architecture, incremental signoff, improved engineering productivity, SmartHub interface, and 3D-IC design efficiencies.

“Today’s design teams often spend five to seven days per iteration to meet chip-level signoff timing and power requirements, and previous methodologies failed to deliver the team collaboration and user experience needed for efficient design closure,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “We are intensely in tune with the needs of the design community, and with the release of the new Cadence Certus Closure Solution, we’re offering our customers a novel environment for chip-level optimization and signoff that delivers exceptional PPA results within a matter of hours. With this new Cadence solution, we’re empowering customers to achieve productivity goals and deliver products to market faster.”

The Cadence Certus Closure Solution supports the company’s Intelligent System Design strategy, which enables design excellence.

 

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