Cadence Digital Full Flow Accelerates GUC’s Time to Tapeout

Article By : Cadence Design Systems Inc.

GUC was able to accelerate the time to tapeout of its ASIC designs by leveraging the Cadence Innovus Implementation System.

Global Unichip Corp. (GUC) used Cadence Design Systems Inc.’s digital full flow to accelerate the time to tapeout of its ASIC designs for mobile, automotive, AI and hyperscale computing applications. By leveraging the Cadence Innovus Implementation System’s mixed-placer automation technology, GUC successfully reduced floorplan design time from weeks to days and achieved more than 10% reduced wirelength and 5% better switching power.

GUC has been using the Cadence digital full flow for many years to tape out the most challenging ASIC designs down to the latest 5nm and 3nm process nodes. As a leading global ASIC provider, delivering the best power, performance and area (PPA) results within ever more demanding schedules is critical for success.

As ASIC designs grow in size and complexity, the number of macros in a floorplan also increases rapidly, making GUC’s traditional manual and iterative floorplanning process a lengthy part of the implementation schedule. Using the Innovus mixed-placer technology, the GUC team can handle the placement of both standard cells and macros concurrently, automating the floorplanning process to achieve greater efficiency and faster PPA analysis.

The Cadence digital full flow provides customers with a fast path to design closure and better predictability. It supports the company’s Intelligent System Design strategy, enabling SoC design excellence.

 

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