Cadence Design Flows Now Certified for TSMC’s Latest N4P and N3E Processes

Article By : Cadence Design Systems Inc.

TSMC has certified Cadence's digital and custom/analog design flows for the latest N4P and N3E processes.

Cadence Design Systems Inc.’s digital and custom/analog design flows have been certified to Taiwan Semiconductor Manufacturing Co. Ltd’s (TSMC) latest N4P and N3E processes in support of the new Design Rule Manual (DRM) and FINFLEX technology. Through continued collaborations, the companies have also delivered the corresponding N4P and N3E process design kits (PDKs) to accelerate advanced-node mobile, AI and hyperscale computing design innovation. Customers have already started using the latest TSMC process technologies and certified Cadence flows to accomplish optimal power, performance and area (PPA) goals and speed time to market.

The Cadence and TSMC R&D teams worked together closely to ensure the digital flow met TSMC’s advanced N4P and N3E certification requirements. Cadence’s complete RTL-to-GDS flow includes the Innovus Implementation System, Quantus Extraction Solution, QuantusFS solution, Tempus Timing Signoff Solution and ECO option, Pegasus Verification System, Liberate Characterization Solution, Voltus IC Power Integrity Solution and Voltus-Fi Custom Power Integrity Solution. The Cadence Genus Synthesis Solution and predictive iSpatial technology are also enabled for the TSMC N4P and N3E process technologies.

The digital full flow offers several key capabilities that support the TSMC N4P and N3E process technologies, including native mixed-height cell row optimization from synthesis to signoff engineering change orders (ECOs) for optimal PPA; standard-cell row-based placement; implementation results that are well-correlated to signoff for faster design closure; enhanced via pillar support for better design performance; large libraries containing many multi-height, voltage threshold (VT) and drive-strength cells; timing robustness cell characterization and analysis; reliability modeling using aging-aware STA; and CCSP model enhancements providing improved accuracy and simplified characterization for analysis via the Voltus IC Power Integrity Solution.

The Cadence Virtuoso Design Platform—which includes the Virtuoso Schematic Editor, Virtuoso ADE Product Suite and Virtuoso Layout Suite—and the Spectre Simulation Platform—which includes Spectre X Simulator, Spectre Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS) and the Spectre RF Option—have been certified for the TSMC N4P and N3E processes. The Virtuoso Design Platform uniquely provides a tight integration with the Innovus Implementation System, which augments the implementation methodology of mixed-signal designs via a common database.

The custom design reference flow (CDRF) has also been enhanced to support the latest N4P and N3E process technologies. The Virtuoso Schematic Editor, the Virtuoso ADE Suite and the integrated Spectre X Simulator help customers effectively manage corner simulations, statistical analyses, design centering and circuit optimization. The Virtuoso Layout Suite has been tuned for efficient layout implementation, leveraging a row-based implementation methodology with placement, routing, fill and dummy insertion features; enhanced analog migration and layout reuse functionality; integrated parasitic extraction and EM-IR checks; and integrated physical verification capabilities.

“By continuing to work closely with Cadence, we’re ensuring that customers can use our most advanced N4P and N3E technologies and the certified Cadence digital and custom/analog flows with confidence,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “This joint effort combining TSMC’s technology advancements with Cadence’s leading design solutions helps our mutual customers meet the stringent power and performance requirements and quickly launch their next-generation silicon innovations to market.”

“Through our longstanding collaboration with TSMC, we’ve continued to keep our focus on creating new technologies that enable our mutual customers to achieve their PPA and productivity goals,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “Our latest work with TSMC reaffirms our commitment to helping customers achieve design excellence with our flows and TSMC’s advanced technologies, and we’re always amazed by the innovations they create.”

The Cadence digital and custom/analog advanced-node solutions that have been tuned for TSMC’s N4P and N3E process technologies support the Cadence Intelligent System Design strategy, which enables customers to achieve system-on-chip (SoC) design excellence.

 

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