Cadence and UMC Collaborate on 22ULP/ULL Reference Flow Certification

Article By : United Microelectronics Corp.

Cadence's digital full flow has been optimized and certified for UMC's 22ULP/ULL process technologies to accelerate consumer, 5G, and automotive application design.

Cadence Design Systems Inc.’s digital full flow has been optimized and certified for United Microelectronics Corp.’s 22ULP/ULL process technologies to accelerate consumer, 5G, and automotive application design. The flow, which incorporates leading implementation and signoff technology for ultra-low power designs, enables mutual customers to deliver top-quality designs and achieve a faster path to tapeout.

The Cadence digital full flow that has been optimized for use on UMC’s 22ULP/ULL process technologies includes the Innovus Implementation System, Genus Synthesis Solution, Liberate Characterization, Quantus Extraction Solution, Tempus Timing Signoff Solution, Litho Physical Analyzer and Physical Verification System. Some of the flow’s key capabilities that enable 22ULP/ULL design are as follows:

• Best-in-class design implementation and optimization engines: The engines are fully integrated from RTL to GDSII, enabling users to achieve power, performance and area (PPA) goals and reduce time to market.
• Optimal signoff convergence: Cadence offers the only digital flow with fully integrated place-and-route, timing signoff, physical verification and IR drop/power signoff capabilities, which provide unparalleled last-mile design closure with the fewest iterations to facilitate the timely delivery of advanced-node products.
• Low-power standard cell library development and characterization: UMC replaced its incumbent library characterization tool with Cadence Liberate Characterization, which is the foundation of the broader digital full flow and a critical piece that enables advanced timing and power analysis, optimization and signoff flows.

“Our 22ULP/ULL platform is ideal for a wide variety of semiconductor applications, including power- or leakage-sensitive consumer chips and wearable products that require longer battery life,” said Y.H. Chen, director of the IP Development and Design Support Division at UMC. “By collaborating with Cadence, we’re providing access to our latest process technologies and Cadence’s robust digital full flow, which enables our customers to meet stringent design requirements and achieve design and productivity goals.”

“Through our latest collaboration with UMC, our mutual customers can adopt our certified digital reference flow and UMC’s 22ULP/ULL low-power technologies and begin design work immediately,” said Kam Kittrell, senior product management group director in the Digital & Signoff Group at Cadence. “This certification allows UMC customers to leverage the most advanced low-power tool feature sets for synthesis, place-and-route, and signoff, enabling customers to design innovative applications with confidence.”

The Cadence digital full flow provides customers with a fast path to design closure and better predictability and supports the company’s Intelligent System Design strategy, which enables advanced-node system-on-chip (SoC) design excellence.

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