The AWR V16 advances heterogeneous technology development for 5G wireless and connected systems for automotive, radar systems and semiconductor technologies.
Cadence Design Systems Inc. has announced AWR Design Environment Version 16 (V16) with groundbreaking cross-platform interoperability to support RF to millimeter wave (mmWave) intellectual property (RF IP) integration for heterogeneous technology development across the industry-leading Cadence Virtuoso design platform as well as the Allegro PCB and IC package design platforms.
The V16 release also introduces seamless integration with the Clarity 3D Solver and Celsius Thermal Solver, delivering unconstrained capacity for electrothermal performance analysis of large-scale and complex RF systems. The new AWR Design Environment, including Microwave Office circuit design software, enables customers to efficiently design 5G wireless and connected systems for automotive, radar systems, and semiconductor technologies and get to market faster. Platform and solver integration in the V16 release provides up to a 50% reduction in turnaround time (TAT) compared to competing workflows.
“To win today in the highly competitive 5G/wireless markets, customers are demanding solutions that enable complete and comprehensive RF workflows that don’t just start and stop at the chip but extend to the entire system,” said Vinod Kariat, corporate vice president of research and development at Cadence. “The RF workflow innovations enabled by the AWR Design Environment V16 release start with a foundational advance in the way design data and software IP are now shared and seamlessly transferred across products. Under the overarching Cadence umbrella, the level of RF integration being introduced with this release is truly an advancement for engineering team productivity.”
Platform interoperability is crucial to expediting RF integration and promoting engineering productivity. Seamlessly sharing design data among the AWR Design Environment, Virtuoso, and Allegro platforms eliminates any disconnect between RF design and manufacturing layout teams, saves valuable engineering resources and positively impacts development schedules. With the V16 release and its deep electromagnetic (EM) and thermal embedded analyses, customers are seeing more than a 3X reduction in TAT.
Key features in this release include:
“Cadence platforms such as the AWR Design Environment, Allegro PCB/SiP, and Virtuoso RF with integrated EM solver technologies are critical to the development of our RF/mmWave MMIC, RFIC and multi-chip 2.5/3D packaging technology,” said Florian Herrault, group leader, Advanced Packaging Solutions at HRL Laboratories. “Our design team is very excited by the performance and productivity gains to be had through Cadence’s RF solutions. Having the ability to share RF IP created in Microwave Office with our IC, package and board teams is driving a significant reduction in our overall design time so we can deliver the highest quality products to market faster.”
AWR Design Environment V16 supports the Cadence Intelligent System Design strategy, enabling system-on-chip (SoC) design excellence and system innovation.