Axelera Unveils AI Test Chip

Article By : Sally Ward-Foxton

AI chip startup Axelera's digital in–memory compute core will be tiled for its upcoming product.

AI chip startup Axelera has tested and validated a chip as a test vehicle for its Thetis digital in–memory compute core. The company’s tests show the 12–nm chip can achieve 39.3 TOPS with a power efficiency of 14.1 TOPS/W in an area of 9mm2.

The test chip was taped out in December 2021, after an impressive four months’ design and verification, with the support of Imec.IC–Link, a European application-specific integrated circuit solutions provider that is part of research institute imec.

This test chip is a proof of concept for Axelera’s digital in–memory compute design, though the company has expertise in both digital and analog compute for AI acceleration (as well as RISC–V design), Axelera CEO Fabrizio Del Maffeo told EE Times.

Axelera test chip
Axelera’s test chip has successfully demonstrated its Thetis core (Source: Axelera)

Axelera also has access to an imec analog computing technology which can achieve “thousands of TOPS/W,” Del Maffeo said, but networks need to be fine–tuned as small variances in analog components can affect the result.

“We have [analog computing] expertise, but we are also exploring interesting in–memory computing and other designs,” he said. “For our first product, the solution we’ve found is that since we want to target high precision and no retraining, it’s good to stay in the digital domain, but get the efficiency you typically get from being in the analog domain, with the same high throughput per area.”

The company’s tests revealed 39.3 TOPS of AI compute with an efficiency of 14.1 TOPS/W at INT8 precision when operating at 800MHz. Throughput can be traded off energy efficiency via clock frequency; at the chip’s highest operating frequency, 970MHz, the performance reached 48.16 TOPS. Peak energy efficiency—enhanced by taking advantage of highly sparse activations — reached 33 TOPS/W with the same test chip (operating at a different frequency).

Axelera’s test chip was one compute core; the company’s first product will be a multi–core design. The company previously said it would target “hundreds of TOPS” for its first product and this is still the plan.

“It won’t be a large number of cores, because we don’t need it,” Del Maffeo said. “The throughput we have and the efficiency we can reach… for edge applications, a few cores is enough.”

The company’s first markets will probably be the highly fragmented industrial, retail, and robotics AI industries, especially customers based close to home in Europe — this primarily includes medium–volume companies who don’t have extensive AI expertise in–house.

Fabrizio Del Maffeo
Fabrizio Del Maffeo (Source: Axelera)

“TOPS and TOPS/W are great, but it’s not enough,” he said. “To win this market we have to deliver performance, usability, and price. In–memory compute can deliver on price because of its throughput per area… but that’s true only if you can solve the problem of usability.”

“For edge computing, 99.5% of customers have no clue what quantization is, and they don’t care,” he added. “They want to know if they can run their networks quickly on our chip — quickly means push a button and make it work.”

Axelera currently has 53 employees spread around Europe, including clusters in Eindhoven, The Netherlands; Leuven, Belgium; and Zurich, Switzerland. The company, incubated by BitFury since 2019, currently has 53 employees and expects to expand to around 65 this summer.

Axelera plans to announce its first product in the autumn ready for delivery to early–access customers in early 2023.

This article was originally published on EE Times.

Sally Ward-Foxton covers AI technology and related issues for EETimes.com and all aspects of the European industry for EE Times Europe magazine. Sally has spent more than 15 years writing about the electronics industry from London, UK. She has written for Electronic Design, ECN, Electronic Specifier: Design, Components in Electronics, and many more. She holds a Masters’ degree in Electrical and Electronic Engineering from the University of Cambridge.

 

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