The Leo CXL Memory Accelerator Platform allows a CPU to access and manage CXL-attached DRAM and persistent memory.
Many vendors are getting their feet wet in the pool of the Compute Express Link (CXL) ecosystem. Accelerators are part of it, and that includes Astera Labs’ recently announced memory accelerator platform for CXL 1.1/2.0.
Leo is designed to address processor memory bandwidth bottlenecks and capacity limitations, said co-founder and chief business officer Sanjay Gajendra in an interview. The Leo CXL Memory Accelerator Platform allows a CPU to access and manage CXL-attached DRAM and persistent memory, making the use of centralized memory resources more efficient and allowing that access to scale up without slowing down performance.
He said Astera’s Leo platform increases overall memory bandwidth by 32 GT/s per lane and capacity up to 2TB whiling maintaining ultra-low latency. It features to scale operations in the cloud reliably while also providing built-in management and diagnostic that large scale enterprise and cloud server deployments require. Gajendra said a lot of discussion today is around bandwidth needing to grow in data centers to handle the volume, but the complexity has been growing just as fast. “The complexity actually doubles every three and a half months.”
That complexity is being driven by more mainstreaming of artificial intelligence (AI) and machine learning in the cloud, which is a big part of why Astera exists. It was founded in April 2018 to solve CXL-like problems before the interconnect was introduced, such as how to connect accelerators and other chips designed for specific workloads, including AI. “The way they need to be connected is very different than what was traditionally done.” That led to a collaboration with Intel to develop Astera’s CXL technology, Gajendra said. The company recently opened a design center in Toronto.
Realizing the vision of AI in the cloud requires a compute architecture where there’s multiple kinds of processes that includes general-purpose processors and ones that can address unique workloads. Because these processes produce and consume a lot of data, cache coherency becomes especially important. Having introduced Aries CXL retimer technology last year that helps double bandwidth and lower latency with the server, Astera is turning to address the bandwidth bottlenecks from server to switch and from switch to switch, said Gajendra.
The company solves these challenges its new Taurus Smart Cable Modules (SCM), which solve the reach, signal integrity and bandwidth utilization challenges for 100G/Lane Ethernet connectivity for Switch-to-Switch and Switch-to-Server applications, he said. The modules support 200/400/800G Ethernet rack connectivity and include advanced fleet management capabilities such as security and extensive diagnostics features. “The alternative to this will be an optical cable, which tends to be four to five times more expensive than a regular copper cable.”
The Leo platform, meanwhile, is what the company believes is the first memory accelerator platform based on CXL that allows a system integrator to expand memory for a single processor pool and share them so that a centralized memory is available for different processes, said Gajendra. The on-demand capabilities assigned memory as needed, which increases utilization and thereby reduces total cost of ownership. Previously, the only way to add memory was to add a second processor, not because the application requires another processor, he said, but because that was the only way in which more memory channels could be added. “It was a very expensive optional memory expansion.”
It could often mean that memory gets unused because it was in the wrong place, said Gajendra. The advantage of provisioning on demand means a central memory resource can be built and memory can be checked in and out as needed. “You can start seeing how CXL makes so much of sense in terms of provisioning on demand.”
Astera was one of many companies demonstrating CXL offerings at Supercomputing ’21, including established vendors and other startups, many of which employed the 1.1 iteration released in 2019. CXL 2.0 came out earlier this year. The industry consortium responsible for development of the CXL specification recently signed a letter of intent to absorb assets of the Gen-Z Consortium, and the transition is expected to be complete by next summer.
This article was originally published on EE Times.
Gary Hilson is a general contributing editor with a focus on memory and flash technologies for EE Times.