Applied Materials and Singapore's IME will extend research via a combined $210 investment aimed at advancing hybrid bonding technology.
Applied Materials and the Institute of Microelectronics (IME) have signed a five-year extension of their partnership focused on heterogenous chip integration research. The extension would continue R&D projects aimed at accelerating advances in hybrid bonding materials, equipment and process technologies.
In 2011, Applied Materials and IME, part of Singapore’s Agency for Science, Technology and Research, established their first joint Center of Excellence in Advanced Packaging. The Singapore-based lab initially focused on 3D chip packaging and fan-out, wafer-level packaging during its first five-year agreement in 2016.
The latest extension includes a combined investment of $210 million, bringing total spending to $460 million. New funding will be used to expand the joint lab by an additional 3,500 square feet. It will also allow the partners to expand the lab’s current research team by 20 percent, according to IME.
Heterogenous IC integration with hybrid bonding
The partners said the extended research project would help drive breakthroughs in heterogenous integration and advanced packaging for innovations in semiconductor design, accelerating the AI era of computing.
“Creating breakthroughs in heterogeneous integration and advanced packaging is a key element of Applied Materials’ strategy to be the PPACt enablement company for our customers,” said Prabu Raja, general manager of Applied Materials’ semiconductor products group. The partners “look forward to accelerating hybrid bonding technology and further innovations in 3D chip integration technologies for the semiconductor and computing industries.”
In September, Applied Materials announced three new technologies to advance heterogenous chip integration processes, including die-to-wafer hybrid bonding, wafer-to-wafer bonding and advanced substrates. Applied Materials and IME both claim their research could further advance those technologies as well as emerging 3D chip integration technologies.
Die-to-wafer hybrid bonding can increase I/O density and shorten wiring lengths between chiplets with direct, copper-to-copper interconnect, thereby improving performance, power and cost.
Wafer-to-wafer hybrid bonding would allow chipmakers to design devices on a single wafer, while other chip structures can be built on a second. The two wafers can then be bonded to boost yield and performance.
Advanced substrates, such as those that use panel-level processing technology, could allow chipmakers to fit greater numbers of chips into 2.5D and 3D designs. Applied Materials panel-sized substrates include 500nm by 500nm or larger sizes designed to reduce cost while improving power and performance.
This article was originally published on EE Times.
Stefani Munoz is associate editor of EE Times. Prior to joining EE Times, Stefani was an editor for TechTarget and covered a host of topics around IT virtualization trends and VMware technologies.