AP Memory is collaborating with Synopsys to deliver optimized and scalable RAM memory solutions for next-gen IoT applications and devices.
Taiwan-based AP Memory Technology Corp. is collaborating with Synopsys to deliver optimized and scalable RAM memory solutions for next generation IoT applications and devices. The solution delivers validated interoperability between the AP Memory’s IoT RAM and Synopsys’ DesignWare Synchronous Serial Interface (SSI) IP.
The Synopsys DesignWare IP offers high transfer rate and low latency in serial memories for IoT and mobile applications. Future collaborations will extend the solution to support even lower power, low pin count solutions such as 1.2V I/O IoT RAM (OPI and HPI), as well as AIOT RAM (15pins – 2.1GBps). AIoT RAM supports the low pin count of IoT RAM with higher performance (~5x bandwidth) and lower active power, targeting Edge AI applications.
AP Memory’s IoT RAM builds on a rich set of PSRAM features that offer low signal pin count, low power and high transfer rate options to meet the demanding power and form factor constraints of IoT and mobile applications. Synopsys’ DesignWare SSI IP will enable designers and developers to make the most out of the potential of AP Memory IoT RAM product line which is scalable from the QSPI (6~7 pins – 72MBps~166MBps), to the well-known OPI (11 pins – 500MBps) and up to the most advanced HPI (20pins – 1GBps) PSRAMs.
“AP Memory is delighted to collaborate with Synopsys. Together, both companies will accelerate development of IoT endpoints and deliver optimal extended memory solution to fulfill the ultimate endpoint experiences,” said Ivan Hong, Vice President and General Manager of IoT Business Unit of AP Memory.
“Our close collaboration with AP Memory provides mutual customers with a comprehensive memory solution that meets the required low-power and memory performance needs of IoT designs,” said John Koeter, Senior Vice President of Marketing and Strategy for IP at Synopsys. “The interoperable solution allows SoC designers to accelerate their time-to-market while minimizing integration risk for SoCs requiring energy-efficient, high-performance memories.”