Advanced Packaging For More-than-Moore Era

Article By : Majeed Ahmad

Chip scaling has reached the point of diminishing returns. The next phase of semiconductor innovation will focus on integrating a myriad of chip components. Our Advanced IC Packaging Special Project looks at the challenges and the opportunities...

Semiconductor packaging has never been more critical. What’s driving the next generation of IC packaging? What does the ongoing disruption in multi-die advanced packaging look like?

Our Special Project examines advanced IC packaging technologies, looking at the road ahead for a critical manufacturing capability that could help revive flagging western chip makers.

Transistor scaling is running out of steam, making advanced IC packaging another manifestation of engineering black magic. Layer after layer of transistors are being stacked in 2.5D and 3D packages while technology behemoths like Intel Corp and Taiwan Semiconductor Manufacturing Co. strive for tighter integration between process and packaging technologies.

In the “More than Moore” era, process engineers need to understand next-generation integration technologies while back-end engineers build extremely dense packages. System-level design engineers also need more clarity on this tectonic shift in the semiconductor world.

However, it seems there is little understanding of how this transition will unfold. For instance, what’s on the die versus what’s on the package?

What are the fundamentals for designing advanced packages?

EE Times’ sister web site EDN, has compiled a special section dissecting the advanced IC packaging challenge.

Gareth Kenyon provides a detailed treatment of heterogeneous integration technology and how it enables semiconductor device manufacturers to combine functional components from different manufacturing process flows into a single composite device.

Ravi Mahajan, an Intel Fellow, makes the case for tighter integration between process and packaging technologies, explaining how heterogeneous integration could help achieve this goal.

Based on an interview with Georgia Tech’s Arijit Raychowdhury, Junko Yoshida’s examines the need for tighter integration between semiconductor processing and packaging technologies. Raychowdhury also notes memory innovations that could propel silicon integration as scaling declines.

Rich Quinnell takes a close look at the FOWLP technology and it place in the advanced packaging world, explaining its face-up and face-down variations. Like stacked IC packaging, FOWLP solutions have exploded during the past decade.

Viewing IC packaging from an EDA perspective, Keith Felton provides an update at the new initiatives such as digital twins for virtual prototypes. He also explains concepts like precision manufacturing handoff and the “golden signoff.”

The special section wraps up with a glossary of fundamental terms in the engineering literature that create a new vocabulary for advanced IC packaging. Knowing these basics can help engineers understand the ongoing disruption in the packaging technology arena.

Articles in this AspenCore Special Project:

Heterogeneous integration enables advanced IC packaging

By Garth Kenyon

The integration of separately manufactured components into a higher-level assembly provides enhanced functionality and improved operating characteristics.


Ask the Expert: Q&A with Process Engineers

By Junko Yoshida

The new frontier of leading-edge IC design is packaging, according to Arijit Raychowdhury, an expert in digital and mixed-signal design who teaches VLSI courses at Georgia Tech.


Package and system designer collaboration will maximize system performance

By Ravi Mahajan

Advanced packaging technologies improve performance of heterogeneously integrated IPs on the package and…


Advanced packaging could help solve chip I/O limitations

By Rich Quinnell

Advanced techniques such as FOWLP allow increased component density, boost performance, and help address chip I/O limitations.


A new approach to IC packaging design

By Keith Felton

For many applications, the next-generation IC packaging is the best path to achieve silicon scaling, functional density and heterogeneous integration while reducing the package size.


10 basic terms for advanced IC packaging

A brief synopsis of the 10 most frequently used terms associated with advanced IC packaging technologies.




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