Quantum tunnelling effect reduces mask steps, slashes lead time.
A collaboration between a British startup and a British foundry has produced test devices of a new transistor type that can be produced with just three weeks’ lead time, as it requires only eight mask steps.
By comparison, the CMOS process typically requires many more mask steps and takes around 15 weeks, said the developers of the technology, Search For the Next (SFN) and Semefab.
Circuit symbol for the Bizen
(Bipolar-Zener) transistor showing the input
which uses the quantum tunnelling effect.
The Bizen process is named for its combination of a bipolar junction with concepts from a Zener diode. It uses the quantum tunnelling effect to eliminate the resistor, and all metal layers, from a traditional bipolar transistor. The transistor’s input is via a quantum tunnelling connection and the device has two identical outputs, allowing for AC signals (anodes 1 and 2; analogous to collector and emitter in a bipolar junction transistor or BJT). The transistor is normally on; bringing the tunnel to the highest potential turns it off.
“The new transistor is as different to a BJT [bipolar junction transistor] as a MOSFET is to a BJT,” said David Summerland, CEO, SFN. “Where the MOSFET has an isolated gate with no direct connection to the n well, in the same way, the Bizen transistor has no direct metal connection to the base well, or to what you would call the base connection in a BJT. The [gate] is isolated, [the connection] is formed by quantum tunnelling.”
The quantum tunnelling connection is created using the principles of a Zener diode — an abrupt change in doping between p and n layers, in which the valance and conduction bands overlap, which generates a quantum current.
In fact, multiple gates can be created in the same transistor, in an effect SFN calls “multi-tunnel.” Multiple NOR and OR gates can thus be created from a single Bizen transistor, allowing creation of logic circuits with many fewer devices. This can result in a three-fold increase in gate density with a corresponding reduction in die size for integrated circuits based on the transistors. Summerland said that SFN is also creating a reduced device count processor architecture to enable analogue computing with Bizen transistors.
A comparison between NOR gates created by (left) a single Bizen transistor, (center) CMOS transistors (note that the left hand side of the circuit is for ESD protection, which is not required by the Bizen version), and (right) the equivalent circuit in TTL. (Image: SFN)
SFN and Semefab also claim the Bizen transistors can match or beat the switching speed and dynamic power of CMOS process technologies (though Summerland concedes there is some static power requirement). Bizen also does not suffer from CMOS’ electrostatic discharge (ESD) susceptibility and latch-up problems.
“Bizen transistors perform at least as well as CMOS,” Summerland said. “But instead of complex structure and high layer counts, especially for power devices, we keep that down to eight layers, so we can produce devices comparable to CMOS in two to three weeks. There have been processes in the past with lead times of two to three weeks, but they were superseded by CMOS because CMOS had very high integration and low power; it was a designer’s dream.”
Bizen devices can be produced quickly and economically at relatively large process nodes suitable for low capex fabs based in the UK. While all current Bizen devices have been produced by co-developers Semefab in Scotland, SFN said that the process would also be transferrable to fabs such as Plessey (GaN) in England and Newport Wafer Fab (compound semiconductor) in Wales.
Both digital transistors and power devices are available using the Bizen process.
The digital devices can in fact be created with only four layers, Summerland said. Switching voltage for these is between 200 and 400mV, suitable for high speed logic applications that require low dynamic power consumption.
“If you are incorporating [digital Bizen transistors] into a power device, you don’t need any plasma metal edge whatsoever,” Summerland said. “Contact windows can be large, pitch can be large, you can use thick, wet edge metal to produce economical computerised power devices.”
Increasing to eight layers brings high power, high current switching capability.
The original aim was to create a chip with a low number of mask steps that could have both logic and power transistors on the same die, with the original intention of creating an LED driver IC. Summerland hit upon the idea of using the reverse bias characteristic of a Zener diode, which is produced by the abrupt change in doping levels between the n and p layers of the diode. This results in the generation of a quantum current. Summerland wanted to use that current to drive a bipolar transistor.
“What came out of that is actually a very elegant process architecture with relatively few diffusions and only eight masks,” said Allan James, Managing Director, Semefab. “Eight masks can create Bizen devices capable of performing logic functions, also lateral devices which are capable of performing analogue functions, and also the vertical npn power transistor function.”
Semefab has processed multiple batches of test devices to establish the necessary diffusion profiles of integrated transistors for logic and power, which are now undergoing detailed characterisation for performance over temperature and other tests. The results, due in the next few days, will inform the next process development run, which will take just two to three weeks, James said.
Equivalent flip flop circuits showing the space saved using Bizen transistors (right) and CMOS MOSFETs (left). (Image: SFN)
“It’s worth mentioning that these process steps are bread and butter, fundamental semiconductor process operations,” he said. “There’s nothing particularly difficult about any of the process steps – they are conventional diffusions, depositions, ion implantations and so on – it’s just the configuration and the doping profiles that enabled this low mask count technology to be developed.”
Semefab, established in Glenrothes, Scotland for 33 years, operates three fabs including two MOS/bipolar facilities (one processing 100mm wafers at the 1µm node, and one processing 150mm wafers at the 1µm node with stepper capability down to 0.7µm), plus a specialised MEMS fab.
The foundry will run further Bizen tests, increasing the level of integration and performing further characterisation including accelerated life testing. Yield statistics, said James, are also not yet available, but he pointed out that so far the Bizen transistors have appeared uniform across their 150mm wafer and that sampling large numbers of devices at random indicated that this is a uniform effect.
Regarding the technology’s potential for scalability, James said that the nature of the individual process steps gives the technology an innate ability to scale to smaller nodes.
“Semefab’s intention is to work with another Scottish facility that has a fine line width lithography capability, down to 0.35µm, to prove scalability by around the middle of 2020,” he said.
SFN is working on a process development kit (PDK) for the technology, plus Bizen standard libraries which Summerland expects to have ready by Q2-2020.
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