TSMC provided a peek at its plans for packaging three-dimensional chips that push performance higher, power consumption lower and transistor density further as Moore's Law loses steam.
The world’s largest foundry joined with partner Arm to announce their new 7nm chiplet system using TSMC’s advanced packaging at TSMC’s Open Innovation Platform Ecosystem Forum in Santa Clara, Calif., last week.
The proof-of-concept chiplet system was made with multiple Arm cores and TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) packaging to demonstrate technologies for building a high-performance computing SoC operating at 4GHz in a 7nm FinFET process.
Rather than the typical SoC with system components arranged on a single die, a chiplet system is optimized for modern HPC processors that partition large multi-core designs into smaller chipsets. This approach allows each chiplet — each die in a package of multiple dice — to be built in different process technologies. The approach is expected to deliver better yields and overall cost-effectiveness.
Cliff Hou, vice president of Technology Development for TSMC, speaks at a company presentation in California last week.
“This demonstration chip is an excellent showcase of the system-integration capabilities we offer to our customers,” Cliff Hou, vice president of Technology Development for TSMC said in a presentation at the event.
TSMC’s CoWoS packaging and LIPINCON inter-chiplet interface enable customers to partition large multi-core designs into smaller chiplets that deliver better yield and better economics, he added.
For high performance, chiplets must communicate through dense, high-speed, high-bandwidth connections. Accordingly, the TSMC/Arm chiplet system features a unique low-voltage-in-package-interconnect (LIPINCON) developed by TSMC that reaches data rates of 8Gbps per pin with what TSMC claims is excellent power efficiency.
The TSMC/Arm announcement comes as other leading chipmakers such as Samsung and Intel roll out their own 3D packaging technologies.
“TSMC has the most advanced semiconductor nodes in production, and that gives them some advantages from a silicon side,” TechSearch President Jan Vardaman told EE Times. “From a packaging side, each company has an approach that could deliver a similar solution, with TSMC and Intel releasing the most information so far.”
The industry is moving in the direction of hybrid bonding, according to Vardaman. Hybrid bonding has many names including direct bond interconnect, or Cu to Cu bonding, but in essence, it means joining devices without the use of a bump, she says.
The TSMC/Arm system is a dual-chiplet implemented in 7nm, with each chiplet containing four Arm Cortex-A72 processors and an on-die interconnect mesh bus. The die-to-die inter-chiplet connection features scalable 0.56pJ/bit (pico-Joules per bit) power efficiency, 1.6Tbps/mm² (terabits per second per square millimeter) bandwidth density, and 0.3V LIPINCON low-voltage interface reaching 8GT/s (giga transactions per second) and 320 Gpbps bandwidth.
The chiplet system was taped out in December 2018 and produced in April 2019.
The system demonstrates for SoC designers an on-die, bi-directional interconnect mesh bus operating at 4 GHz, and a chiplet design methodology using an 8Gbps chiplet interconnect over a TSMC CoWoS interposer.
TSMC provided more details on its expectations for its 3DIC packaging technologies in press briefings at the Santa Clara event.
CoWoS will keep expanding physically, according to Douglas Yu, TSMC vice president of Integrated Interconnect and Packaging. The current reticle size of 835 mm² will soon double, he says.
The company also aims to grow interposer size for its InFO packaging. InFO is a wafer-level system integration technology featuring high density RDL (re-distribution layer) and TIV (through InFO via) for high-density interconnect and performance. InFO includes various packaging schemes in 2D and 3D that are optimized for specific applications.
TSMC will soon integrate 10 chiplets as well as a wafer-size chip using InFO, according to Yu.
To back up that claim, TSMC had on hand Cerebras Systems vice president Dhiraj Mallick at the event. With TSMC, Cerebras made a wafer-size chip with more than 1 trillion transistors and 400,000 computing cores manufactured on a 16 nm process as Cerebras pursues its goal of building a fast computer optimized for AI that’s 1,000 times faster than the best-in-class.
“Big chips process data more quickly,” said Mallick. “Memory is just one clock cycle away from compute core.”
(Source: EE Times)
TSMC has still more packaging plans in store with SoIC, which Yu calls a game changer.
SoIC is a bumpless packaging technology that’s different from the rest of the industry, which is using micro bond techniques for 3D assembly, he says.
TSMC’s SoIC is a front-end wafer-process that integrates multi-chip, multi-tier, multi-function technologies to enable high speed, high bandwidth, low power, high pitch density, and minimal footprint for 3DIC integration.
The technology also enables off-chip heterogeneous system-level scaling, according to TSMC.
The closer proximity of one chiplet to another through SoIC provides advantages of lower latency and reduced power consumption, according to Yu.
Longer term, TSMC sees a shift from chip partitioning to what it calls deep partitioning.
Some parts of a chip such as I/O are more difficult to scale in silicon and therefore need to be partitioned out, allowing other parts to scale down. Yu says multiple chips packaged in up to three layers with SoIC are in the works.
The combination of SoIC with InFO promises to accelerate density gains, according to TSMC. The company also is working on combinations of SoIC with InFO.
The company expects the first product made with its SoIC technology in the fourth quarter of 2020.