5G: It’s Not Just a Mobile Network!

Article By : Tektronix and Keithley Experts

It takes more than just the 5G mobile phone and network to enable the entire 5G revolution. This article highlights some examples that enables 5G, the updates and associated challenges.

5G development and deployment are accelerating, especially in Asia. Field trials are underway, components are coming, and testing covers the spectrum in more ways than one. What are the challenges and how is the ecosystem shaping up? Find out more in this month’s In Focus series.

For a while now, we keep hearing about 5G deployment and devices in the news. In our mind, we usually think about the next 5G mobile phone from your favorite brand. A few of us would know that it takes more than just the 5G mobile phone and mobile network to enable to entire 5G revolution.

In this article, we will highlight some examples that enables 5G, the updates and associated challenges.

Powering the 5G Revolution

All electronics starts operating from a power source. As the devices evolve in 5G, the very power source that runs 5G needs to be upgraded as well. The latest buzzwords in power semiconductors are the wide bandgap devices, powered by silicon carbide (SiC) and gallium nitride (GaN).

While we take so much for granted, many engineers and scientists are working every day with materials like SiC and GaN to develop power electronic systems that will drive the new 5G revolution, components and modules for hybrid and electric vehicles, military and aerospace systems, and power systems for computing and consumer products. But what is the significance of SiC and GaN, and how do you handle the testing challenges we are facing with these materials?

After years of research and design, SiC and GaN power devices are becoming more viable. The shift to SiC and GaN is driving new designs from the ground up. SiC, with its capability of driving high power at high voltages for high power applications, and GaN, with its super high-power density for medium to low power applications, are pushing the limits of what is possible with silicon-based designs in efficiency and power density. For example, SiC is finding applications in higher power, higher voltage designs such as motor drives in automobiles, locomotives, and PV inverters. GaN technology is also shaking up the world of RF power amplifiers, thanks to many of the same attributes that make it well-suited for power conversion. GaN is carving its niche in data-center power, wireless power, consumer power supplies, and automotive and military/government power electronics.

EE Times Asia 5G Webinar: Leveraging New Opportunities and Ecosystems in a 5G World

Experts from Qualcomm, Rohde & Schwarz, Keysight Technologies, Movandi, EdgeQ, Infineon, and SPIL will share their insights and strategies—from the testing challenges, to semiconductor design and packaging, all the way to deployment and new applications and services—to stay ahead of this rapidly growing mobile technology.

Click here to register!

These devices, though high-performance, come with challenges for designers. Setting cost and reliability aside, these power devices are not drop-in replacements for their silicon counterparts. Semiconductor R&D engineers are working to validate and characterize new components. Driver manufacturers are developing new gate drivers to withstand the demands of faster switching, EMI management, and more sophisticated topologies. Manufacturing engineers in these companies are dealing with wafer testing challenges – having to thoroughly test smaller devices over wider voltage and current ranges than ever.

Manually characterizing wafer and package-part level devices for electrical performance requires learning new techniques, equipment, and probing infrastructure for low level measurement (e.g., pA of leakage current measurement in the presence of high breakdown voltage).

Some of the biggest challenges working with SiC and GaN devices are the gate drive requirements. SiC requires much higher gate voltage (Vgs) with a negative bias for turn off. GaN, on the other hand, has much lower threshold voltage (Vth), requiring tight gate drive designs. Wide band gap (WBG) devices, by the nature of their physics, also have a higher body diode voltage drop that requires much tighter control of dead-time and turn-on/turn-off transitions.

Solving these challenges may be tough for us. It is critical that we have accurate electrical source and measure testing when characterizing these high voltage devices so that the right design decisions can be made in a timely fashion. Increasing design margins and overdesigning will only drive costs up and bring performance down. And, due to the high voltages involved—usually >200 V—keeping the scientist and engineer safe from harmful voltage is very important.

Increasing the performance of data processing, transfer, and storage

From augmented reality to artificial intelligence, cloud computing to IoT, 5G is fueling growth in new technologies—and the data they create. Besides new CPU, GPU, ASICs and FPGA that drives the data processing, other parts of the system evolve along too.

With more and more data comes the need for storage and fast access, which means that technology like DDR5 has never been more important. The need for data centers to continuously store, transfer and process this data pushes the limits of high-speed signaling and ushers in testing challenges not seen in memory to date.

DDR5 is very different from DDR4 and is more like LPDDR4. Check out these nine changes that DDR5 brings to the table:

• It’s faster! First and foremost, data rate goes up to 6.4 Gbps, whereas DDR4 stopped at 3.2Gbps. There’s also a provision in the spec to push the speed limit beyond 8Gbps in the coming years. The channel structure is similar to LPDDR4, where we have two independent 40 bit channels with ECC. We also have higher prefetch, higher burst length and increased bank groups. This is all to increase the efficiency and enable high-speed modes
• Another big change in DDR5 is that writes are not center aligned. There’s a fixed offset between DQS and DQ. What that means is we cannot just measure the delay between DQS and DQ on the scope and figure out whether it’s read or write. That luxury is gone. Read-Write burst separation is all set to be more complicated.
• New clock jitter measurements. DDR5 introduces Rj, Dj and Tj measurements in place of period and cycle to cycle jitter measurements. Specifications of Rj are very tight at the maximum data rate. Good signal integrity will be paramount to measure these parameters with confidence.
• De-embedding is going to be critical at higher DDR5 data rates. De-embedding is a technique to remove the probe and interposer loading. It is also used to move the probe point virtually from DRAM ball to the DRAM die to minimize reflections. We want to see what the Rx is seeing. To successfully create de-embedding filter files or transfer function, s-par files are required – lots of them. Idea is to mimic the DDR channel as faithfully as possible by using s-par models for SOC package, board models, DRAM package, interposers, probes as well as IO settings like Tx drive strength and Rx ODT (if applicable). In the absence of s-par models, one can also use simple transmission line parameters like propagation delay and characteristic impedance by measuring the reflection on the scope screen.
• For the first time we will have Rx equalization, 4-Tap DFE, in the receiver. The increase in the data rate in DDR5 is achieved without moving the DQ bus to differential signaling i.e. the DQ bus is still single-ended—same as DDR3/4. However, memory channel has lots of impedance mismatched points which increases the overall ISI due to reflections. At data rates above 4,800Mbps, the data eye at the DRAM ball is expected to be closed. A 4-tap DFE is implemented in the DDR5 DRAM Rx to help equalize the DQ signals and open the data eyes after the data is latched by the receiver. Furthermore, RCD’s CA Rx will also need DFE to ensure reliable signal capture.
• Another dramatic change for DDR5 is the inclusion of a loop back channel. If you look at the pin map of DDR5, you will find dedicated DQS/DQ loop back pins. This will be used to enable standalone DRAM RX/TX characterization. A loop back channel is critical. In fact, it is how we know what bit decision a receiver actually makes in real time. It’s a single wire that’s shared between all the different receivers, and because it has poor signal integrity and for that and other reasons, it’s why we only send back every fourth bit or every second bit, so that there’s plenty of time to be able to make sure that an outside receiver or bit error detector can check with 100% accuracy the quality of the on-die Rx.
• There is a need for standalone DRAM Rx/Tx testing in DDR5 using a BERT and/or a flexible pattern generator. This opens a whole new suite of tests including voltage & frequency sensitivity and stressed eye tests that were not present in DDR3/4. Concept is a simple one – anyone should be able to use the standardized JEDEC fixture, follow JEDEC defined test procedure and perform standard tests to determine the health of DRAM Rx/TX.
• Accurate stress calibrations are going to be a big issue in DDR5 RX testing, and that is getting accurate S-parameter models, both ones that you’ll have to estimate as well as measure for all the segments. Another critical feature will be being able to make accurate or good guesses for the measurement depths and the oscilloscope record sizes, so that you’re not wasting too much time.
• DRAM Rx/Tx testing will present a huge database management problem. Automating and managing the massive amounts of s-par files, de-embedding models, and measurement results is going to be a nightmare. Imagine testing 80+ pins at different speed grades for multiple DIMM configurations from different vendors. That’s going to be very, very hard.

High Speed Serial Buses

Next generation innovations are bringing with them next generation challenges. High-speed communication between subsystems within the hardware is often based on the well trusted PCI Express bus. As the PCI Express standards progress from Gen 4 (16.0 GT/s) to Gen 5 (32.0 GT/s), engineers face a variety of new validation challenges from the doubling of data rates:

• Overcoming higher channel loss and inter-symbol interference (ISI)
• Designing silicon and platforms to operate with smaller margins in more constrained environments
• Debugging at both the physical and protocol layers
• Keeping pace with the next generation of data rates and storage standards requires end-to-end solutions that can scale to 32.0 GT/s while providing current-gen capabilities designed and maintained by industry experts.

Optical Super-Highway

With 5G, the amount of data transacted is grow over 50% by 2025. The drives rapid worldwide growth and demand for high-performance datacenter infrastructure and cloud computing. To keep pace with this relentless demand, developers are transitioning to 400G technologies enabling smaller, faster, lower cost-per-bit solutions.

There are several core technologies that are enabling 400G or even 800G, including the use of higher order modulation and higher data rates up to 56 GBaud. This new modulation scheme provides four-level pulse amplitude modulation (PAM4), which transmits two bits per symbol, doubling the data rate compared to conventional NRZ.

PAM4 signals, having a lower signal-to-noise ratio and one-third of the amplitude of equivalent NRZ, require more advanced tools and features for successful validation.

One of the greatest challenges is keeping test cost per device as low as possible while meeting required specifications. With PAM4 signals increasing the number of tests needed to conduct versus NRZ signals by a factor greater than 10, solutions providing measurements quickly for optimized tuning, with the lowest noise to maximize production yields are required.

Evolution at the consumer end of 5G

The consumer computing industry also demands a new form of IO’s that can deliver on a vision of future needs. These needs include improved video and audio quality, such as 2K, 4K, and 8K displays, shrinking of the system form factor so that we can design thinner, lightweight laptops, and flexible performance. Thunderbolt technology meets the competing demands of a convenient standards-based, multifunctional small form factor, and of course, faster data rates.

Fundamentally, Thunderbolt is a tunneling architecture designed to take a few underlying protocols and combine them into a single interface so that the total speed and performance of the connection can be shared between the underlying usages of these protocols. Whether they are data, display or something else, Thunderbolt 1 and 2 built on a mini-DisplayPort connector and deliver the physical data rate of 10Gbps. By aggregating two lanes Thunderbolt 2 doubles the data to 20Gbps. Now, Thunderbolt 3 builds on a USB Type-C connector and doubles the data rate again to 40Gbps in each direction by aggregating two lanes of 20Gbps. Thunderbolt 3 supports the basic USB 2.0 and USB 3.1 power delivery modes. In short, Thunderbolt 3 offers the best single cable docking solution.

The Thunderbolt 3 specification was released to USB-IF for royalty-free use in the development of USB4 specification. Now, Thunderbolt 4 and USB4 products will use the same underlying protocol specification. Thunderbolt 4 offers the maximum data rate of 40Gbps bi-directional and offers the same 15W to devices or 100W of charging power.

The Thunderbolt 4 system requirement is 32Gbps of data using four lanes of PCIe Gen-3. If you talk about the electrical verification of Thunderbolt 4, then it’s the same as Thunderbolt 3. From an end-user perspective, Thunderbolt 4 peripherals will have four ports—one up-facing-port (UFP) and three down-facing-ports (DFP). The Thunderbolt 4 cable can work with any of the USB-C ports and can support Thunderbolt 3, USB 2.0 or USB 3.1/3.2 and DisplayPort Type-C devices.

Next Generation applications

5G is also expected to drive several new applications that requires smart communication between end nodes and the wider smart environment. Smart estates will have next generation of IoT enabling predictive maintenance, smart monitoring, waste, and energy management.

Manufacturing will be even more connected with artificial intelligence and smarter robotics to increase both efficiency and effectiveness. Mobility in both land and maritime can expect to get smarter with more data sharing for more advanced tasks to be automated and better managed.

Putting next generation technologies together

5G is a buzzword we hear these days, but the underlying technologies that enables 5G is often under-estimated. With the myriad of new technologies assuring that the entire ecosystem works starts with understanding the changes in the complexity. The complexity to enable them gives rise to new test challenges.

Measurement need not be a necessary evil. With a good set of measurement, characterization tool and knowledge, engineers now know why the device fails and what made it went well. We can now double down on our strength and learn from the mistakes with knowledge and data provided by good measurement plans and tools. At the same time, measurement tools have also evolved to be more automated via software and cloud. This has made life of engineers so much easier.

These evolution in tools enable engineers to have data on hand in a quicker and systematic way to analyze and collaborate. These learnings and data then become the foundation of our key to build and engineer a better future.

Subscribe to Newsletter