Packaging and interconnect are critical to achieving wireless systems that perform “better than wired”...
Gary Hilson recently offered insight into the memory requirements of AI hardware. As products move toward tighter integration of memory and AI processors through advanced packaging and interconnect techniques, we are again thinking about chiplets. For processor to memory, there is less system diversity, and industry standard communication interfaces are expected, but there are challenges and limitations nonetheless. These limits will provide the roadmaps for AI and HPC, and more work is needed to optimize the trade-offs between memory density, data exchange bandwidth and power consumption. But more of the heterogeneous — i.e. more functional diversity — is related to networking, 5G and IoT.
Although we are on the cusp of the big AI revolution and the HPC memory challenges it entails, the unwired generation has only just begun. We often think of the wireless revolution starting so long ago that it must be over by now. First we had the wireless LAN connection for our clunky old laptops (that no one really wanted to haul very far from the Ethernet connection anyway). Many early-century technologies followed. Some we are just learning to live with. Bluetooth gave us wireless keyboards, mice and headphones as well as speakerphone connections for our vehicles. Don’t get me wrong. These are all worthwhile conveniences, especially now that the connections tend to be a little less troublesome than they were in the early days. But these were all means of separating regular consumers from their cash for a little extra convenience. There was never an ROI calculation.
The RAN chairman of 3GPP noted that 5G for factory automation would have to be “better than wires.” He was speaking of performance, and they working groups developing wireless specs will make sure that happens. The flexibility, ease of adaptation and ROI compared to hardwiring probably offer enough value to changeover or at the very least 5G implementation for new builds.
On that front, Skyworks has announced a very diverse system-in-package (SiP) integration with its SKY66430-11 “5G Massive IoT SiP” product. Skyworks bills it as the “World’s Smallest 5G Massive IoT Solution.” At the same time massive and the world’s smallest, the full evaluation kit implementation requires only code storage flash and a few passives beyond the package. This SiP integrates digital, RF, and memory chiplets (if you will) in the package, specifically these:
This is the complete baseband to RF, needing little more than power and an antenna in an encapsulated BGA package 8.8 by 10.8 by 0.95 mm.
Skyworks see this product as an entry into tracking of assets, people, and pets. As 5G coverage improves and this translates into blanketing indoor spaces as well, this type of tracker will have a market. You might think being asked to carry a tracker diminishes your worth, but take heart. At least someone out there considers you an “asset.”
Getting back to the intelligent systems at the other end of the wireless data path that might credit you as an asset, CEA-Leti recently announced a collaboration with Intel to improve processors with 3D packaging technologies. The research will focus on high performance computing applications (HPC). As announced, this is the assembly of “smaller chiplets” and the optimization of the interconnect between them. One could think of smaller chiplets as another step in the evolution from system-on-chip to system-in-package for HPC as more designs adopt the chiplet mentality.
The Leti announcement recognized the June 2020 IEEE Electronic Components and Technology Conference award for the best paper of the previous conference awarded to a long list of co-authors. The focus of the paper (available to subscribers at IEEE) was the first successful chiplet integration using an active silicon interposer.
The Leti announcement refers to Intel’s Foveros 3D package technology. The Foveros concept was often touted as the use of an “active” as opposed to a passive interposer to interconnect different types of die in a microprocessor. The interposer was also referred to as a bridge to interconnect the chiplets.
Leti touts other areas that are well-known and common concerns for entities developing 3D packaging for HPC including bonding and stacking techniques. But the gist of the paper – especially grabbing the award – is based upon the active interposer. The long list of authors was exclusively CEA-Leti, none from Intel. That’s not too surprising since the paper was written more than a year before the collaboration announcement. But it looks like the French research offered Intel something quite attractive – the active interposer.
This is where it gets confusing if you have read some of the press on Intel 3D packaging. At some point in this game of telephone, the “active interposer” was slipped into the discussion about Intel Foveros. There’s no one in marketing playing fast and loose with terms. This is simply a conflation of information that often comes out of the media blender.
So the net-net when all is said and done is that the CEA-Leti advanced packaging engagement with Intel will primarily be about active interposers. That’s what Intel is looking to next.