Next-generation IC packaging is the best path to achieve silicon scaling, functional density, and heterogeneous integration while reducing the overall package size.
For many applications, next-generation IC packaging is the best path to achieve silicon scaling, functional density, and heterogeneous integration while reducing the overall package size. Heterogeneous and homogeneous integration technologies offer a path to enhanced device functionality, faster time to market, and silicon yield resiliency.
Multiple integration technology platforms have emerged that allow for cost, size, performance, and power optimizations to satisfy the needs of multiple markets, such as mobile computing, automotive, 5G, artificial intelligence, augmented reality and virtual reality, high-performance computing, IoT, medical, and aerospace. However, these packages present unique challenges for traditional package design tools and methodologies. Design teams must work together to verify and optimize the entire system, not just the individual elements.
Traditional IC packaging substrate design is typically very similar to a small-scale laminate and/or buildup-based PCB. It is often manufactured by traditional PCB fabricators and is usually designed with modified PCB tools. In contrast, today’s advanced packages use manufacturing techniques, materials, and processes that increasingly have more in common with silicon foundry processes and require a new approach for design and verification at all levels.
One of the first challenges a design team must overcome is the accurate aggregation of substrates — which can be both active and passive — and discrete devices. These substrates and devices come from multiple sources and suppliers and, most likely, are available in multiple and often different formats.
It is therefore clear that a comprehensive verification flow is required — one that accounts for assembly-level physical verification as well as more in-depth, system-level electrical, stress, and testability verification. Also needed are design tools that deliver fast, accurate, and automated flows to ensure that market schedules and performance expectations can be met. Ideally, these flows provide a single integrated process built around a 3D digital model, or digital twin, of the entire heterogeneous package assembly.
These next-generation IC packages need a next-generation design and verification solution that incorporates and supports:
• Digital prototyping
• Multi-domain integration
• Scalability and range
• Precision manufacturing handoff
• Golden signoff
Digital twin for virtual prototype
Building a digital-twin, virtual model of a 2.5D/3D heterogeneous assembly provides a comprehensive representation of the full system comprising multiple devices and substrates. The digital twin enables automated verification of heterogeneous assemblies beginning with substrate-level design rule checking (DRC) and expanding into layout versus schematic (LVS), layout versus layout (LVL), parasitic extraction, stress and thermal analysis, and, finally, test.
Model construction requires the ability to aggregate data from different sources and in different formats into a cohesive system representation suitable for driving verification and analysis. Ideally, this is done using industry-standard formats such as LEF/DEF, AIF, GDS, or CSV/TXT files. Functionality should also exist in a way that automatically recognizes device and substrate interfaces without having to instantiate pseudo-components. This allows for multi-designer asynchronous design and verification. That, in turn, ensures overall system success when all components are completed and integrated.
A primary benefit of the digital-twin approach is that it serves as the golden reference to drive complete physical and electrical verification at every level of the design hierarchy. That eliminates the multiple, static spreadsheets typically used to represent pin and connectivity information, replacing them with a full, system-level netlist in Verilog format.
The preservation and reuse of original data, such as a device’s Verilog description, are key. The biggest risk comes when translation or conversion occurs, such as with a schematic or spreadsheet. If this is done, the “digital thread” is immediately broken, and the risk for connectivity errors skyrockets.
A digital-twin methodology also enables multi-domain and cross-domain integration. Bringing more complex advanced IC packages to market faster requires highly integrated design and verification — from electronic substrate design to mechanical package heat-spreader and PCB-mounting hardware, including the interrelated aspects of electrical, thermal, test, reliability, and, of course, manufacturability. Without a system-level approach to design and verification, engineers risk experiencing costly re-spins or worse.
Synchronization of electrical and mechanical information is essential to ensuring that no physical violations occur when a package is placed within an enclosure or an entire system. The incremental exchange of data during design is fundamental to ensuring ECAD-MCAD compatibility and increased first-pass success. It also aids in the creation of more robust designs while increasing productivity and achieving faster time to market.
It is extremely important that both the IC package designer and the custom heat-spreader designer can visualize, explore, and optimize the integration, ideally as an asynchronous process that minimizes cross-domain interruptions.
Synchronization between package design and mechanical/thermal design is also a significant challenge to first-time–right success. Heterogeneous multi-substrate packages exhibit multiple chip-package interactions. One of the largest is thermal dissipation, especially of the non-linearly generated heat typical in such packages.
A typical approach to thermal management uses a heat spreader for heat transfer and dissipation. But a heat spreader is only as good as its design. For the heat spreader to be efficient and effective, it must be designed and simulated in conjunction with the package, not as an afterthought. Designing the entire package in 3D ensures efficacious heat-transfer realization without significant design compromises.
Both 2.5D and 3D stacking can create a variety of unintentional physical stresses, such as substrate warpage during mounting and bump-induced stress. Designers must be able to analyze a layout for stresses caused by such chip-package interactions and their impact on device performance. Once the package is nearing implementation completion, the accurate 3D packaging thermal model can be exported for inclusion in detailed PCB and full-system thermal analysis. This enables final tuning of the system enclosure and allows natural and/or forced cooling to be optimized.
Advanced IC packages bring many new challenges for signal integrity engineers and their design tools. Dies are mounted directly to the substrate, so it becomes possible to couple substrate routing with on-die redistribution layer routing.
Packages are no longer simple, planar layer structures with easily modeled, simple vias between metal layers. Instead, there can be multiple substrates of very different materials and properties. Analysis can be used successfully for a number of signal- and power-integrity–related items.
In addition, a number of items are challenging to simulate. These generally fall into the category of electromagnetic interference (EMI). While these return-path–created EMI issues can be analyzed and simulated, it’s normally not productive to do so. For example, in the case of a trace crossing a split in a plane, simulation setup and run times will be considerable, and all engineers will learn is that such situations are bad and should be avoided.
Such issues are best identified through software-automated, geometry-based inspection and checking during design. These can be typically set up and executed in minutes, with issue areas clearly highlighted for remedial design action. Such a “shift left” approach prevents issues from being created in the first place, making EMI analysis more of a verification signoff step.
The 2.5D and 3D heterogeneous designs typically use through-silicon vias (TSVs), which are long vias extending through the die or substrate to connect the front and back sides. TSVs allow dies and substrates to be stacked and directly interconnected. However, in addition to their own significant electrical characteristics, TSVs have an indirect effect on the electrical behavior of devices and interconnects in their vicinity.
To model a 2.5D/3D heterogeneous system accurately, a designer needs tools that extract precise electrical parameters from the physical structure of the 2.5D/3D elements. Those parameters can then be fed into behavioral simulators. Utilizing the 3D digital-twin model of the complete package assembly, designers can accurately extract the parasitics of the 2.5D and 3D models. Once the elements have been extracted correctly, using the appropriate methodology and process, they can be assembled into a system-level interconnect model and simulated to analyze performance and appropriate protocol compliance.
Scalability and range
Heterogeneous packaging technologies are more complex to design, fabricate, and assemble, potentially limiting their availability to all but the leading semiconductor companies and their bleeding-edge designs. Fortunately, the design and supply chain ecosystem can play a powerful role in enabling the democratization of such technologies, putting them within the reach of all designers and companies — just as the silicon foundry world did with process design kits (PDKs), which have become ubiquitous.
Automated IC verification is driven by design rules created by the foundry and provided in a PDK to design houses. EDA tool suppliers qualify their toolsets against these rules to ensure their verification tools produce proven, repeatable, signoff-quality results. The purpose of a package assembly design kit (PADK) is similar to that of the PDK: to facilitate manufacturability and performance using standardized rules that ensure consistency across a process.
Obviously, a PADK must include both a physical verification and extraction signoff solution, and it should also address thermal and/or stress signoff solutions. All of these processes should be independent of any specific design tool or process used to create the assembly. In addition, a complete PADK must work across both IC and packaging domains, implying that the flow must support multiple formats. Finally, all of these verification processes must be validated by the package assembly/outsourced semiconductor assembly and test (OSAT) company.
The scale and complexity of advanced IC packages put immediate pressure on the designer and the design schedule, which often gets extended. An emerging popular approach to managing this is concurrent team design, wherein multiple designers simultaneously work on the same design across local or global networks, yet retain the ability to visualize all design activity without having to endure any onerous setup or process management.
Precious manufacturing handoff
Another common challenge is the time required for verification signoff prior to manufacture. The proven way to avoid this bottleneck and its related impacts is to implement a process and methodology of integrated and continuous verification so that the final verification signoff process is controlled and manageable. This means providing manufacturing-error–free fabrication and assembly data that passes the foundry’s or OSAT’s process rules (PDK or PADK). The goal and the challenge are to achieve this in the first pass.
Eliminating iterations requires a design environment with the capabilities and features to meet process rules without relying on hit-or-miss manual methods that will likely require multiple design spins to achieve the handoff criteria. In order to avoid multiple design revisions to pass the manufacturer’s rules, automation is mandatory.
Advanced IC packaging is almost always fabricated using GDSII. It is this GDSII file that the fabricator, foundry, or OSAT will verify for compliance to their manufacturing rules and constraints, which, of course, leads to a common dilemma: The GDSII file is post-processed from the design tool’s native CAD database, and that’s where problems can and do occur.
No matter how well your CAD design tool can produce geometries that meet the manufacturer’s fabrication rules, it’s the post-process–derived GDSII that will be used for signoff, and that’s the Achilles’ heel of most IC package CAD design tools today. The actual design in CAD may pass as compliant, but because of poor-quality geometry post-processing, the resultant GDSII rarely does. That’s what typically leads to design spins as the designer struggles to achieve acceptable GDSII.
For advanced IC packages, golden signoff requires a comprehensive set of checks, or else total assembled device yield will not hit targets and will overrun projected assembly and test costs. Comprehensive golden signoff should include, at a minimum, physical verification, connectivity checking (aka LVS), and heterogeneous assembly-level verification (aka LVL). Such a comprehensive signoff checking process can highlight many issues that require rework. If not detected, those issues can easily delay projects, add costs, and lead to missed manufacturing schedules.
One way to prevent this from happening is to implement a shift-left design flow, performed in-design to locate and eliminate obvious signoff errors. Using such a methodology can remove more than 80% of signoff errors and prevent signoff bottlenecks and delays.
One hallmark of IC verification has been the use of multiple, specialized EDA tools within a single framework to enable designers to perform a wide variety of verification processes. The goal is the same when automating heterogeneous package assembly verification. Heterogeneous verification is significantly simplified based on the premise that each individual die has already been checked against its target foundry rules. It’s also critical to maintain independence between the design and verification environments to ensure the veracity of verification results.
Verification includes DRC to verify the interactions between die components and may require extracting several layers within each die to see these interactions. Physical verification also includes LVL checks for alignment between substrates, scaling or compensation factors, and pad centers or overlaps. For an EDA tool, engineers must understand how to differentiate the layering per die and per placement. Moreover, the tool should leverage the digital-twin virtual model’s data to automatically extract the correct assembly representation in order to perform the DRC and LVL checks.
Connectivity checking — LVS — in an IC looks at the connected shapes and pin locations derived from physical layout data to produce the physical netlist, which is compared against the golden schematic netlist to verify connectivity. Connectivity checking is performed at each substrate level and across substrates. An automated, package LVS flow in its simplest form must ensure that the interposer and package GDSII correctly connect die to die (for multi-die systems) and die to C4/BGA bumps (for both single-die and multi-die systems) as intended by the designer.
The system netlist is compiled from the digital twin of the overall assembly, as discussed earlier. This system or golden netlist is then compared against the physical design connectivity derived from the manufacturing data. The virtual model can highlight warnings or violations, so designers can trace and debug errors with the help of an EDA tool.
The 2.5D and 3D heterogeneous packages typically incorporate multiple devices and multiple substrates to deliver the required solution for system scaling and performance. With decreasing delineation between die and substrate, the proximity of these elements greatly enhances chip-package interactions, necessitating a unified co-design flow. With critical elements like high-speed interfaces or power delivery, a decision on one substrate can have a ripple effect on adjacent substrates or impact the entire system.
Designers must find ways to manage multiple substrates in a single environment while collaborating across geographies and departments, using rapid prototyping and co-design to evaluate substrate routability, electrical and thermal performance, and testing. As methodologies and flows mature, system-level designers also need to know whether package DRC, LVL verification, and assembly-level LVS are sufficient to guarantee correct functionality and successful manufacturing of the heterogeneous assembly.
With a single environment for managing all of these processes in an efficient, repeatable, and automated flow, designers can better anticipate and eliminate potential downstream issues, efficiently perform and evaluate tradeoffs and design scenarios, and clearly communicate decisions to stakeholders.
Finally, known-good–die testing and package-level test generation are critical prior to stacking in 2D and 3D heterogeneous assemblies. Test teams should reuse die-level, built-in self-test, and scan patterns by mapping them up to the package level. Boundary scan testing of the package interconnect structures ensures that the I/Os are actually connected and can identify any substrate fabrication or assembly issues.
Complete design and verification flow
For many applications, next-generation IC packaging is the best path to achieve silicon scaling, functional density, and heterogeneous integration while reducing the overall package size. Integrating multiple devices into a single package supports system scaling demands, reduces system real estate, lowers manufacturing costs, and often increases quality and reliability.
Next-generation IC packaging designs need a new approach for design and verification at all levels, starting with the use of a digital-twin virtual prototype model that drives all aspects of design and verification, even if different design tools are used, enabling designers to manage all of these processes in an efficient, repeatable, and automated flow.
Mentor, a Siemens Business, offers a high-density advanced packaging solution developed specifically to address the five keys to next-generation IC packaging design. This complete design and verification flow integrates the industry’s gold standard in verification. Calibre 3DStack, along with Xpedition Substrate Integrator and Xpedition Package Designer, leverages HyperLynx and FloTherm for cross-domain multi-physics analysis.