250W source paves way for EUV production

Article By : Dylan McGrath

Lithography vendor ASML claims to have achieved an important and long-elusive milestone: the demonstration of a 250-watt EUV source.

The semiconductor industry finally appears close to moving extreme ultraviolet (EUV) lithography into high volume production.

At the recently held Semicon West tradeshow in the United States, lithography vendor ASML announced it had achieved an important and long-elusive milestone: the demonstration of a 250-watt EUV source. Source power—a measurement of the amount of EUV photons delivered to the scanner to enable wafer exposure—equates directly to productivity. Chipmakers have long insisted that source power of 250W would be required to achieve throughput of 125 wafers per hour (WPH) and the inability of ASML and Cymer (which ASML acquired in 2013) to push the technology to hit that mark has been considered the primary roadblock for EUV development in recent years.

Michael Lercel, director of strategic marketing at ASML, said the company has demonstrated 250 watts “rather consistently by really understanding the conversion efficiency in the source and putting the right controls in place.” He said the source that has demonstrated 250W has not yet shipped.

Leading edge chipmakers including Intel, Samsung, TSMC and Globalfoundries are planning to insert EUV into high-volume production sometime in the next two years. ASML demonstrated back in February throughput of 104 WPH and executives said even before the 250W source power was demonstrated that the company had a roadmap to get to 125 WPH.

The 250W source power milestone represents an improvement of 10 fold over the past five years from about 25W in 2012. Delivering a presentation on the economics of EUV for production, Lercel joked that when he worked at Cymer in the early part this decade the goal for reaching 250W of source power “was always next year.”

ASML has 14 development tools already in the field which have now exposed more than 1 million wafers, including more than 500,000 wafers in just the past 12 months, according to Lercel. The first shipments of ASML’s NXE:3400B production EUV tool began earlier this year.

As of April, ASML had a backlog of 21 EUV systems awaiting delivery, the majority of which are reportedly ticketed for Intel. The company is expected to provide an update of its EUV backlog when it announces its second quarter results next week.

The development of EUV can be traced back to the 1970s with the ill-fated development effort of X-ray lithography. The semiconductor industry was originally hoping to use EUV in production early this decade, but development has slipped continually. By some estimates, the industry has spent more than $20 billion on the development of EUV.

Despite ASML’s progress, critics will continue to scepticism toward EUV. “Detractors keep saying it’s never going to happen, but ASML keeps hitting its targets,” said G. Dan Hutcheson, a veteran semiconductor equipment analyst and president of VLSI Research. “It sure has taken a long time, but we finally seem to be getting somewhere.”

In addition to the source power milestone, Lercel also detailed significant improvements on the overlay performance of EUV tools and industry progress on the infrastructure for EUV, including reticles, pellicles and photoresists.

Lercel’s presentation largely focused on the economic value to customers of EUV, an ironic subject given that the cost of the tools—over $100 million each—have been one of the biggest knocks on EUV. But ASML argues that EUV—when it achieves its 125 WPH throughput target—offers an economic benefit compared to the expensive of triple- or quadruple-patterning using immersion lithography tools.

“If you look at the cost of doing multiple immersion lithography steps, coupled with the process steps—the cleaning, the metrology—we believe that EUV is less costly per layer versus triple patterning immersion, and certainly quadruple patterning and beyond,” Lercel said. He added that EUV also offers the economic benefit of faster cycle times, fewer variables and fewer chances for random defects on wafers.

“We believe that EUV is a very cost-effective way to enable the affordable scaling of lithography in the future,” Lercel said. “We have made significant progress on enabling the performance of [EUV] systems to be able to match those expectations, particularly given that the imaging is as expected, the overlay is at least as good as the immersion tools and productivity is now over 100 wafers an hour. That really has enabled the point where we started to go into the point of shipping high volume manufacturing tools out to customers now.”

ASML’s source power milestone announcement comes less than two weeks after the passing of Natale Ceglio, a scientist whose pioneering work in x-ray lasers and EUV was critical to early development of the technology. Ceglio died on July 2.

First published by EE Times U.S.

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