Comprehensive debug, run control and performance tuning in one neat little toolset
MADISON, Wis. — Designing a complex SoC by mixing and matching different semiconductor IP cores is hard enough. The job gets tougher, with higher costs and arduous process of the validation and verification, after the SoC comes back from a fab, according to Rupert Baines, CEO of UltraSoC.
To address such post-silicon woes, UltraSoC, a Cambridge, U.K.-based supplier of advanced debugging and analytic technology for embedded systems, is claiming that it has devised for SoC designers “a complete integrated development environment that combines comprehensive debug, run control, and performance tuning.”
By leveraging technologies from Imperas and Percepio, UltraSoC updated its debugging toolset, now called UltraDevelop 2. It plans to offer “system-level on-chip monitoring and analytics infrastructure” with advanced visualization and machine learning capabilities, according to the company.
Many semiconductor experts blame the rising cost of SoCs on skyrocketing photomask costs. While that’s true, even more worrisome to many semiconductor companies is the expense of verifying and validating an SoC, said Baines.
The crux of the issue is “systemic complexity” in SoCs, Baines told us.
The number of semiconductor intellectual property blocks used on a chip is growing by leaps and bounds. More significant is the growing number of interactions among those blocks.
“These sophisticated, complicated blocks integrated on a chip no longer function independently,” said Baines. “Instead of two processors interacting each other in a linear fashion, several blocks are talking among themselves in 10 or more different ways.” These interactions are “exploding,” among a variety of IP blocks including memory controllers, co-processors and accelerators integrated on an SoC, he explained.
Over the last decade, chip designers have transitioned from designing multicore processors to manycore processors and even heterogeneous multicore processors. While this evolution has been painful, Baines said the situation is becoming even more dire because it is not unusual to find an SoC that integrates several different processor architectures — such as cores from Arm, Ceva’s DSP, GPU and RISC-V.
Because each of these processors comes with its own development tools, the consequence is “a vendor silo.”
“Most CPU IP vendors have tools that report on the functionality of their IP,” said Richard Wawrzyniak, principal analyst for ASIC and SoC at Semico Research Corp. “ARM, for example, has their CoreSight product, which is similar to what UltraSoC has, but only works with their own products.”
Under such an environment, Baines noted, a designer who wants to verify on an SoC must look at one screen to see what’s going on inside its Arm cores, while peeking at another screen to see how Ceva’s DSP core is doing. These tools offer no time stamping. In sum, SoC designers have nary one tool to see in a single view what’s going on with an SoC at a system level.
UltraDevelop 2 allows SoC designers to see real-time actionable insights in a single window. In the photo above, a demonstration board containing an Arm CPU generates a fractal pattern on the screen, while the engineer views the operation of the program via the GUI on his workstation. (Photo: UltraSoC)
UltraSoC’s Ultra Develop2 will change that, promised Baines. “SoC designers can see on one screen what’s going on in Arm, Ceva, memory and interconnect. If you halt an Arm core, for example, you can halt the whole system,” he said.
UltraSoC is pitching its newly updated UltraDesign 2 as a tool to display the status of hardware and software of an SoC “in one, coherent view.”
The integrated system-level view isn’t the only thing UltraSoC offers. Semico’s Wawrzyniak noted that UltraSoC’s tool suite “also performs many additional functions like security and fine tuning of the memory controller / memory interaction and fine tuning of power and power management functions.”
Unlike UltraDevelop 1, an initial “demo grade” version, Ultra Develop 2 is “product grade,” noted Baines. More important, his firm made improvements in the new version by integrating third-party tools from Imperas and Percepio.
The inclusion of Imperas Multi-Processor Debugger (MPD), for example, “enables support for today’s multi-core, multi-threaded platforms, including devices that combine cores based on different CPU architectures into complex heterogeneous systems,” according to UltraSoC. The inclusion of Percepio’s Tracealyzer within UltraDevelop 2 brings “data analytics and visualization capabilities” to the UltraDevelop suite, “marrying the worlds of hardware and software development.”
UltraSoC explained that the Tracealyzer tool “understands” the meaning of high-level events within software or an RTOS, connecting related events and views, and complementing the information gathered via UltraSoC’s hardware monitors.
Data Science extensions
While Baines cautioned that “big data” and “machine learning” are hefty terms that come with high expectations (thus prone to hype), UltraSoC is now applying data science extensions to its debugging toolset. UltraSoC isn’t claiming to be machine-learning experts, Baines said, “We are applying open-source AI capability to specific domains” of SoCs.
He said, “Because of our knowledge of what SoCs are, what’s inside them, what a processor is, and what a bus is, for example, we have a priori understanding [of the SoC domain]. That lets us develop a package for anomaly detection for our customers.”
While running the UltraDevelop 2 program, Baines said, “You simply press the button, and you start hearing ‘ding, ding, ding.’ When our tools see some weird or odd behavior on certain areas of an SoC, such as overflow in memory bandwidth, the tool asks SoC designers, ‘do you really want that?’”
A suit of modules inside UltraDevelop 2 facilitate detailed big data analysis of on-chip behavior, including anomaly detection, heat mapping and root cause analysis, according to UltraSoC.
Baines said, “Some of the cloud guys are already using our tool” to debug chips used in data centers. While not many SoC companies are using AI to validate their chips yet, Baines said NetSpeed Systems, recently acquired by Intel Corp., might be an exception.
Wawrzyniak agreed. “NetSpeed was one company that was using machine learning in their interconnect IP tools, but Intel has acquired them so I’m not sure if this will continue to be licensed to the market or not,” he said. “I think they stated they would service existing customers, but not take on any new customers.”
Pre-silicon vs. Post-silicon
Beyond NetSpeed, Wawrzyniak said, “I believe the large EDA companies are looking at incorporating some AI functionality into their tool suites also.” But he added, “The difference between the EDA companies and UltraSoC is that — so far — the EDA companies are pre-silicon in a virtual world and UltraSoC is post-silicon in the real world.”
Wawrzyniak explained, “UltraSoC is in emulation and prototype, and that is for both lab (bring up, integration, verification, validation) and in life (field trial and operation). This combination provides a much deeper look into the silicon and addresses many of the areas that designers care about.”
He added, “To me, the key difference here is that the UltraSoC approach allows for the analytic functionality to be embedded directly into the silicon instead of existing as a separate function to be applied to the silicon on a different ‘host’ system such as the large EDA companies do.”
He noted, “This is a decided advantage since now the silicon can be accessed and exercised in the field instead of needing to bring it back to a lab to be examined. This cuts time and cost and allows the designers to see what is happening ‘in-situ’ instead of running tests absent of the ‘real-wold’ environment the silicon is expected to function in.”
Designing a chip is only half the job SoC designers must do, according to Baines. Remaining jobs include determining that the SoC is functioning, verifying and validating the SoC, checking whether low-level software – such as drivers – is working and how layers of software on top SoC are working. “You can’t ship a chip without software, so validating everything including software becomes critical,” said Baines.
Indeed, Wawrzyniak singled out as the most significant element of UltraSoC’s products “the ability to cover both the silicon and the software and to provide a ‘system-wide’ view to the customer.” He noted, “This greatly aids in finding and fixing any issues that might pop up once the silicon in in the field. They can scale to support heterogenous multicore or ‘many-core’ designs which has become an important element in many designs today.”
With its ability to flag errors, bugs or anomalies on a chip, UltraSoC has earned the reputation that its tool can be used as a burglar alarm, according to Baines.
Potentially, the tool might be able to flag security gaps in the next Meltdown or Spectre. In fact, some companies are coming to UltraSoC to ask if their tool can spot “a delivered bug,” said Baines. In the cybersecurity world, a system can be compromised by a bug intentionally delivered by hackers. Hence, the system must be able to identify such bugs inserted by design.
Several chips used in data centers, for example, will benefit from UltraSoC tools’ burglar alarm-like functions, said Baines.
Asked if that means that UltraSoC could have detected a suspected “spy chip” that Bloomberg reported had been installed on boards supplied to servers bought by Amazon, Apple and others, Baines said, “If the spy chip is installed in an isolated location, and independently intercepting the signals, it would be difficult to spot it.” But if the spy chip was tampering with code on the main SoCs, thus changing the behavior of the chip, “we could have flagged it,” he said.
Indeed, UltraSoC’s tools are currently used in Fintech applications to ensure that only authorized parties have access and read the secure area of protected memory, for example. They also work in mil/aero, where a system has only a single trusted element that shouldn’t be subverted.
In hopes of increasing developer choice and flexibility, in addition to support extensibility, UltraSoC said that UltraDevelop 2 uses industry-standard interfaces such as the Eclipse Target Communication Framework (TCF), the GDB Remote Serial Protocol (RSP), Common Trace Format (CTF), and MI, a machine interface layer commonly used to communicate between a debugger’s backend and the IDE front end.
Additionally, UltraSoC leverages the OpenOCD project and adds custom extensions to provide debug support through on-chip monitoring and analytics hardware, with results released back to the open-source community for further development.
Baines said that UltraDevelop 2 will be sampling among its lead customers in the New Year, while general availability is slated for the spring of 2019.
— Junko Yoshida, Global Co-Editor-In-Chief, AspenCore Media, Chief International Correspondent, EE Times