Chip business could be worth as much as $1 trillion annually by 2030
SAN FRANCISCO — In a nondescript meeting room high above the exhibit floor at last month’s Semicon West tradeshow here, Ajit Manocha, president and CEO of the SEMI trade group, stood up to address a group of about 25 people, mostly representing test and packaging companies.
In remarks that lasted no more than 20 minutes, Manocha touched briefly on a number of topics, including the now defunct International Technology Roadmap for Semiconductors (ITRS), the economic pull of artificial intelligence (AI) and life beyond Moore’s Law. Manocha also noted the 22% growth in semiconductor sales last year that few could imagine just a few years ago and declared the chip business would be worth $1 trillion per year by 2030.
Depending on who you believe, Moore’s Law has either run out of gas or is sputtering along on fumes. What emerges as the semiconductor industry’s guiding principle in the post-Moore’s Law era is a matter of considerable debate. But, increasingly, engineers and chip firms are eyeing the concept of heterogeneous integration — separately manufactured silicon and non-silicon components integrated into a higher level system in the same three-dimensional system-in-package — as the electronics productivity driver of the future.
The meeting that Manocha spoke at that day in July was in fact a workshop for the Heterogeneous Integration Roadmap (HIR), an IEEE-backed effort to create a pre-competitive technology roadmap outlining a long term vision for HI and identify challenges and potential solutions.
“People need to have some direction,” said Manocha, who went on to tell attendees that SEMI would partner with IEEE to provide stewardship for the roadmap, as well as two other IEEE roadmap efforts, the International Technology Roadmap for Devices and Systems and the International Technology Roadmap for Wide Band-gap Semiconductors. “We will take the responsibility to take the roadmaps to the industry for validation and feedback.”
Since 2016, when the Semiconductor Industry Association (SIA) pulled the plug on the highly regarded and closely watched ITRS, the semiconductor industry has been in a sense rudderless. Without the industry-wide goals and technical targets outlined in the roadmap, leading-edge chip makers have continued to blaze a path the rest of the industry to follow.
“Roadmaps are useful for the entire industry,” said E. Jan Vardaman, a veteran packaging analyst and the founder and president of TechSearch International. “A roadmap gives you an idea of how you get to the next step.”
William T. Chen, an ASE Fellow and senior technical advisor who chairs the HIR committee, said the collaboration involved in creating the roadmap will save everyone in the industry work, likening it to putting in place a structure like the U.S. interstate highway system. “We have a great responsibility to make sure that areas of concern are reflected in the roadmap,” Chen said.
The HIR effort, which began in 2016, aims to identify the requirements for heterogeneous integration in the electronics industry through 2031, identifying challenges and potential solutions. A draft of the roadmap was initially expected to be available last month, but is now expected to be released in mid-October. Plans call for the roadmap to be updated once a year after that.
“It took 50 years to get where we are now,” Chen said. “We need to build a knowledge base. It doesn’t happen overnight.”
Manocha, who formerly served as the SIA’s chairman and vice chairman while he was the CEO of Globalfoundries, was still heavily involved in the SIA when it made the decision to stop publishing the ITRS Roadmap. He told attendees at the July HIR meeting that for many years the semiconductor industry “walked to the direction that the ITRS provided” but that the SIA “dropped the ball in sponsoring the roadmaps.” Now, he said, he and SEMI want to take responsibility for “the ball we dropped at SIA” and steward the roadmaps.
As part of SEMI’s involvement, Manocha now sits on the HIR’s global advisory council. “I provide guidance in defining a long-term vision of technology innovation over the next 15 years,” Manocha told EE Times in an interview earlier this week. He added that part of the role that he and SEMI will play is “to ensure that its value proposition for stakeholders in industry, academia, research institutes and government is understood by and available to all.”
The HIR effort is in many ways more broad in scope than the ITRS ever was. Because the concept of heterogeneous encompasses rapidly evolving design concepts, packaging architectures, device types, materials, manufacturing processes and systems integration technologies, the HIR effort involves participation from throughout the supply chain — chipmakers, materials suppliers, equipment companies, test/assembly providers, EDA firms and others.
Currently the effort involves 22 separate technical working groups (TWGs) that span components, design components, packaging technologies, materials, security, thermal management, supply chain and more.
At the HIR workshop in San Diego in May, Andrew Khang, a University of California-San Diego computer science professor who is well known for contributions to chip design and EDA, noted that the HIR effort also looks at application markets, something that the ITRS never did. The HIR efforts includes six TWGs devoted to applications, including high-performance computing/data center, IoT, medical/health/wearables, automotive, aerospace/defense and mobile.
“When the ITRS was active, they were only looking at one industry,” Chen said. “At the time there was one driving force. But now [electronics has] many driving forces and a diverse landscape.”
For the semiconductor industry, shifting from a perpetual focus on extending Moore’s Law to a world where productivity advances are achieved primarily through heterogeneous integration is no small endeavor.
Bill Bottoms, a pioneer in semiconductor test who co-chairs the HIR committee, pointed to a report on semiconductor research published last year by Semiconductor Research Corp. titled, “Semiconductor Research Opportunities: An Industry Vision and Guide.” Bottoms summarized the report by saying research will enable groundbreaking advancements in applications such as AI, IoT, high-performance computing and the “ever-connected world that society has come to expect and depend upon.”
But Bottoms noted that the bulk of semiconductor R&D has focused throughout much of the industry’s history on the advancement of Moore’s Law. “But the economic end of Moore’s Law, if not already here, is coming. No one disputes that,” Bottoms said.
To move forward, Bottoms continued, new technologies are required. New devices are needed to augment silicon-based transistors. And novel computing architectures must be developed to replace the traditional von Neumann architecture, leading to entirely new computing paradigms.
“We’ve got to work together across industry, government and academia,” Bottoms said. “And we have to work across country boundaries.”
According to Bottoms, while CMOS scaling will continue, the only parameter that is advancing noticeably is density, while cost, power and performance gains are falling short of what was historically expected.
“Heterogeneous integration is the only solution that will allow the Moore’s Lawy pace of progress to be continued for decades to come,” Bottoms said. “Power requirements, latency, cost and performance at the system level are dominated by the interconnect rather than the transistors. Heterogeneous integration enables system level integration in a SiP where all the active functions are as densely packed as possible. Interconnect will be photonic moving the photons as close to the transistors as possible.”
Bottoms listed a number of benefits to heterogeneous integration, including multiple orders of magnitude of performance improvements in the same process node, power reduction through replacing electronic wiring with optical wiring where practical and incremental cost improvements through integrating cost effective components one function at a time.
Bottoms claims that heterogeneous integration at the system level can deliver a more than 1,000X improvement in functional density and reduce power per function by a similar amount. “Initially some of this will come with higher cost,” he said. “But, in the long run, the cost per function will be reduced by 10,000X in the next 15 years with shorter and less expense design cycles.”
But bold claims about the advantages offered by heterogeneous integration remain mostly pie in the sky. For now, the HIR committee is still working to complete the first draft of the roadmap.
At a fundamental level, long before massive benefits in cost per function are achieved, the HIR committee hopes that the roadmap will provide the industry with a common nomenclature as a starting point for laying down technical targets and challenges. There are already a number of examples of heterogeneous integration in the electronics realm — perhaps most notably the second-generation SiP found in the Apple Watch 2, SI 2, which contains more than 42 die. But definitions of terms such as 2.1D, 2DO and 2DS are not uniform throughout the industry.
“We are trying to come up with some common terminology,” Vardaman said. “Terms like 2.5D and 3D are not helpful if they aren’t descriptive and people don’t understand what they mean.”
The committee hopes that a common language will help the industry to roll up its sleeves and get to work. There is, after all, much to be done if heterogeneous integration is to achieve the type of productivity gains that Bottoms and others envision.
“The greatest single breakthrough in the near term will be the integration of photonics into SiP products and efficiently connecting these systems with optical signals to everything else,” Bottom said. “Longer term, co-design, simulation, highly parallel manufacturing, SiP and interconnect standards as well as the development of ensured reliability and security will be needed.”
— Dylan McGrath is the editor-in-chief of EE Times.