Increased number of challenges in IC design as manufacturing processes shrink
IC designs are always shrinking and getting more complex. As line widths and distances between interconnects become ever smaller, IC designers need to verify that designs comply with increasingly more complex design rules. That’s where description languages that check complex patterns play an important role.
Today’s rule-checking languages are running into problems as processes have shrunk below 40 nm and the trend continues down below 20 nm. “As we get more advanced processes, the rules are becoming more and more complex,” said Jerry Frenkil, the Si2 program director of OpenStandards, in a telephone interview with EE Times. “There are more new design rules and more complex rules than ever before. We started running into issues at around 20 nm that were not issues before.”
Si2 fellow Jake Buurma explained further: “Distances between shapes such as wires and vias get smaller and, as where previously a rule looked for distances between shapes, the same distance could now cover several shapes.” Thus, design rules could no longer accurately describe the distances between shapes. Buurma explained how you could have two shapes that have a third shape near their ends. A design rule would have to cover three shapes. Chip designers using older processes might only have to be concerned with the distance between two shapes but now must contend with three shapes in a given distance. Figure 1 shows how, as chip sizes reduce, a rule that describes a given space will cover ever more shapes.
Remember, too, that these distances are in three dimensions. Designers must contend with rules that say you can’t stack more than three vias on top of each other. Another rule, explained Buurma, is that a wire of a certain width might need two vias to connect to another layer. That is, you need redundancy.
Furthermore, you might have a case where the spacing of vias on two wires might be different than the spacing if there are two vias on the same wire. It’s a conditional test, depending on if two vias are on the same wire or two adjacent wires. Furthermore, the voltages on these wires might also force a different design rule to apply. “This conditional checking results in a rules explosion in terms of the number of design rules that are needed to check,” said Frenkil. “It also becomes extremely difficult to describe complex relationships and rules. That’s one of the big issues with design-rule checking (DRC) of today’s semiconductor processes. In addition, different designers can also interpret the rules differently.”
Intel has developed a DRC language called Open Pattern Analysis for Layout (OPAL) that can describe these conditions. According to Buurma, OPAL can describe shapes and it can test for design-rule compliance.
Each process node comes with its own set of unique issues. “Design rules are no longer continuous; they become quantized,” said Buurma. “With 20-nm technology, you can have a ‘forbidden pitch,’ which means that there can be an interval where a certain spacing between two shapes isn’t valid, but either a smaller spacing or a larger spacing is valid.” Figure 2 shows how a 20-nm process has unique distance rules.
Buurma explained, “An OPAL rule called EndToEndComplicated might check if the line end spacing between any two wires are within a specified interval. This is a more advanced spacing check than normal Design Rule Check. At 40 nm, a normal spacing check would verify that the distance between the two wire ends is either equal to or wider than the minimum design rule constraint. In contrast, OPAL can also check if the wire ends are with a user-specified interval of spacing constraints.”
Figure 3 shows another example of OPAL’s pattern-matching capabilities. Buurma explained how OPAL can find user-defined patterns and mark them when they appear in a layout. The ability for a user to define his own search patterns is a major feature of OPAL. The example OPAL code in Figure 3 looks for a user-defined pattern called a “Jet Plane” where the code looks for that specific shape.
Intel has made OPAL available to Si2, which has formed a working group to standardize the language. Working group members can now evaluate the language and suggest edits, cuts, or additions.
Group members may consist of engineers from companies in semiconductor businesses that are different from those at Intel. For example, FinFET processes need different rule checks than planar processes, and microprocessors might require different rules than memory chips.
— Martin Rowe covers test and measurement for EE Times and EDN.