The on-chip memory is picking up at top speed, showing no signs of slowing down as it occupies a significant fraction of system-on-chip (SoC) die area. It is also consuming a big piece of the overall power budget. For example, the automotive memory IC market is expected to more than double, going from $1.6B in 2015 to $3.5B in 2018 (Source: IC Insights 2015). This growth is driven by consumer demand for convenience, additional capabilities, compliance with safety standards, sustainability, etc.

The growth in memory, including reprogrammable non-volatile memory (NVM), is apparent across all types of market segments. Figure 1 shows the two established and mature reprogrammable product categories within NVM – embedded flash and traditional logic-based multi-time programmable. A cost-effective option within the logic-based multi-time programmable category is the zero-mask-adder NVM solution.

zmaf1 Figure 1: Product categories within reprogrammable NVM

Despite several emerging NVM technologies, embedded flash remains the technology of choice for applications that require a few hundred to tens of thousands of cycles of reprogrammability. In addition, embedded flash is an attractive choice for chip designers because of its compact footprint and widespread availability in popular processes and foundries.

As an alternative to embedded flash, designers have historically utilise an external Electrically-Erasable Programmable Read-Only Memory (EEPROM) to bridge the gap in 16k- to 64k-bit counts. EEPROM devices use a serial or parallel interface for data input/output and can be programmed or erased in-circuit by applying special programming voltages. However, this approach adds to the bill-of-material (BOM) cost and requires additional pins and board space. Being an off-chip solution, data security for EEPROM contents also becomes a concern for certain applications. While embedded flash is popular, there are several constraints that merit careful reconsideration:

1. Increased mask cost

In markets like automotive, connectivity, sensor, and analog, cost is a critical factor for ICs implementing functions like analog trimming, storing coefficients & parameters, and small data/code storage. These IC designs require less than 512k bits of reprogrammable NVM. Embedded flash, with its 12 to 14 mask adders, can increase total die cost by 25% to 40%, making it simply too expensive for these designs. New zero-mask-adder NVM architectures can offer increased bit counts up to 512k bits, enabling these ICs to realise lower die cost as compared to embedded flash. Figure 2 shows, with the availability of higher bit counts in zero-mask-adder NVM solutions, ICs needing up to 512kb NVM can now realise a lower cost than embedded flash.

zmaf2 Figure 2: ICs needing up to 512k bits can achieve lower cost using zero-mask-adder NVM solutions.

2. Slower performance

Low-end MCUs generally require performance up to 25MHz and low power embedded flash macros can struggle to meet the required 40ns read times. This results in additional wait states for the MCU, lowering energy efficiency. The addition of cache/shadow RAM is also undesirable as it results in extra area and power consumption. In recent years, zero-mask-adder NVM architectures have improved program/erase and read timing. Some processor vendors now offer a dedicated configurable NVM interface to simplify system integration, making the sub-40ns reprogrammable logic NVM a viable alternative.

3. Incompatibilities (of embedded flash) with processes needed for PMIC applications

Bipolar CMOS DMOS (BCD) is a well-established target technology for most Power Management ICs (PMICs), combining the benefits of three different functionalities onto a single chip:

  • Bipolar for precise analog functions
  • CMOS for digital design
  • Double-Diffused Metal Oxide Semiconductor (DMOS) for power and high-voltage elements

Supporting embedded flash on a BCD process poses a manufacturing problem. The embedded flash process steps are completed early in the wafer manufacturing process due to the additional heat cycles (anneals) required for bit cell devices. However, the high-voltage DMOS transistors also require early heat cycles to keep from impacting the underlying CMOS/logic devices. Tuning the heat cycles without embedded flash and DMOS impacting one another becomes challenging. If the BCD process requires only one flavour of DMOS devices, then the ‘cumulative’ heat cycle approach may be feasible, but in reality, commercial foundries are forced to support a wide variety of devices for applications with different voltage ranges. For this reason, embedded flash on a BCD process can be challenging and costly to manufacture. A zero mask adder NVM can be implemented on BCD processes without any additional implants or processing steps, making it an ideal solution for PMIC applications.

With recent improvements in design, reliability, and lower test cost, zero-mask-adder reprogrammable NVM is now a feasible alternative to embedded flash for a broader range of ICs. For example, smart algorithms embedded within zero-mask-adder reprogrammable NVM can handle bit-to-bit mismatches needed to support larger memory arrays. The traditional need for a differential or 100% redundant reprogrammable NVM bit cell approach has given way to improved single-ended bit cell architecture which offers a more competitive area footprint vs. embedded flash macros.

In summary, overall memory on an SoC, including NVM, is growing to meet several requirements including consumer demand for feature-rich devices. In the reprogrammable NVM space, embedded flash and zero-mask-adder NVM have been the mainstream options. Embedded flash is popular but has major drawbacks for use in cost-sensitive IC designs needing less than 512kb densities. The 25-40% mask-adder cost, incompatibility with PMIC applications, and performance constraints, are the major impediments for use of embedded flash in automotive, connectivity, sensor, and analog IC markets. With improved design, reliability, and test-cost considerations, new zero-mask-adder NVM solutions have the capability to address these cost sensitive markets with bit counts up to 512k bits.

—Faisal Goriawalla holds a Master of Science Degree in Electrical and Computer Engineering from North Carolina State University and is Product Marketing Manager for Synopsys’ DesignWare NVM IP and Embedded Test and Repair.