Xilinx extends SDSoC development environment that enables software-defined programming of the 16nm Zynq Ultrascale+ MPSoC.
Xilinx releases the SDSoC development environment, enabling software defined programming for the Zynq family of SoCs and multi-processing (MP) SoCs using C and C++ languages.
The new release includes support for the recently introduced 16nm Zynq UltraScale+ MPSoC. Additionally, this release enables a significant leap in productivity through system level profiling tools and by reducing the compilation time in half.
"The SDSoC development environment has ramped quickly to over 650 users; many of them getting to market very quickly with production Zynq SoC-based designs," said Nick Ni, senior manager of SDSoC product marketing and planning at Xilinx. "In addition to Zynq Ultrascale+ MPSoC support, we have dramatically reduced compilation time, and the time to eliminate system level performance bottlenecks."
Systems and embedded software engineers can leverage the SDSoC development environment to easily program Zynq UltraScale+ MPSoC devices. At the click of a button, SDSoC automates the acceleration of C/C++ functions from the ARM application processor unit into the FPGA fabric by generating custom hardware IPs using High Level Synthesis (HLS), hardware connectivity, software drivers and application executable files.
Unlike traditional siloed embedded software and hardware development flows that can result in development delays and uncertainty in system architecture and performance, SDSoC is architected to provide system profiling and architecture exploration, in a familiar Eclipse IDE framework. This release adds real-time system-level visibility into performance bottleneck using hardware and software event trace monitors.