FDSOI, standing for fully depleted silicon on insulator, is an alternative to the FinFET chip manufacturing style favoured by Intel and foundry TSMC. Much of the original research for SOI was conducted by IBM before being carried forward by STMicroelectronics. Now Samsung at 28nm and Globalfoundries at 22nm are working to bring FDSOI into production. The companies claim that FDSOI, despite more expensive engineered wafers as a starting point, offers advantages in terms of scalability from low-voltage, low-power up to high performance.

The 12FDX process nominally at 12nm minimum geometry, is intended to enable the intelligent from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles. It is notable that FDSOI missed out on a design win with automotive chip developer Mobileye that was attracted to 10nm FinFET.

The 12FDX process provides a step up in performance and avoids the need for triple- and quad-patterning and extreme ultraviolet lithography, said Rutger Wijburg, general manager of Globalfoundries' Dresden wafer fab where FDSOI is being developed. "If you look at performance with back-bias 22FDX is the same or better than 16/14nm FinFET process. With 12FDX with back bias you get better than 10nm FinFET processes," he told EE Times Europe.

In short, 12FDX offers performance of 10nm FinFET with better power consumption and lower cost than 16nm FinFET.

"Some applications require the unsurpassed performance of FinFET transistors, but the vast majority of connected devices need high levels of integration and more flexibility for performance and power consumption, at costs FinFET cannot achieve,” said Globalfoundries' CEO Sanjay Jha, in a statement. "Our 22FDX and 12FDX technologies fill a gap in the industry’s roadmap by providing an alternative path for the next generation of connected intelligent systems."

Customer tape-outs of 12FDX circuits are expected in the first half of 2019.

FDXcelerator

Alongside the announcement of 12FDX Globalfoundries announced the FDXcelerator program to ease migration to 22FDX from bulk nodes such as 40nm and 28nm planar CMOS.

Initial FDXcelerator Partners have committed to provide EDA tools that complement industry leading design flows by adding specific modules to easily leverage FDSOI body-bias differentiated features.

Features include basic, foundation and interface and complex IP. The partnership will also provide reference solutions, design consultation and services and product packaging and test solutions.

Initial partners are: Synopsys (EDA), Cadence (EDA), Invecas (IP and design solutions), Verisilicon (ASIC), CEA-Leti (services), and Encore Semiconductor (services).