Today's car manufacturers are focusing their innovations on the sophisticated cockpit electronics that improve driver safety and the overall driving experience. More and more consumers are factoring a car's advanced driver assistance systems (ADAS) and infotainment features into their buying decisions. These systems combine several features that require heavy-duty signal processing, such as forward-looking smart cameras for detecting and classifying objects, back-up camera electronic control units (ECUs), and head-unit centre information displays, to name a few. As a result, they require higher current power supply regulation at low voltages. The buck regulators in these systems must generate point-of-load (POL) voltages as low as 0.6V for the GPUs, FPGAs, DSPs and other higher current devices receiving their power from a 5V or 3.3V primary supply rail as shown in figure 1. Several clever IC design choices have yielded a new generation of 3A, 4A and 5A synchronous buck regulators able to address the varying load requirements from entry-level to luxury automobiles. To help system designers understand their benefits, it is useful to understand the architectural choices made when developing these fully integrated devices, as there are many different ways to implement a buck regulator. This article examines the asynchronous buck versus synchronous buck configuration. We'll also discuss the trade-offs N-channel or P-channel transistors used for the switches in the synchronous buck configuration. We'll then look into a family of 3A, 4A and 5A sync buck regulators, and show how their wettable flank QFN packages pass visual inspection during the printed circuit board (PCB) assembly process.

EEOL 2016JUN13 TA 01Fig1* Figure 1: Typical automotive power supply architecture.*

The asynchronous buck regulator
As you can see in figure 2, the asynchronous buck DC/DC converter has one switch (S1) that is driven on and off to control the duty cycle ratio. The circuit includes a diode that acts as a secondary switch when the potential across it causes forward biasing. When switch S1 is on, the input voltage is connected to the inductor, causing current to build up in the inductor until switch S1 is shut off. When S1 is switched off, the current flowing through the switch to the inductor is interrupted.

EEOL 2016JUN13 TA 01Fig2 Figure 2: Asynchronous Buck Implementation.

However, due to the nature of the inductor, the current flowing through it wants to continue flowing in the same direction. For this to happen, the voltage polarity across the inductor changes, allowing the current to flow through in the same direction. When this occurs, the diode is forward biased, allowing the pass through current. Regulation of the output voltage is performed by feedback (not shown in figure 2) to control the duty cycle of switch S1.
The synchronous buck regulator
The synchronous buck DC/DC converter is illustrated in figure 3. In this configuration, the diode is replaced with a switch. The switch is a field effect transistor (FET), which is designed to have very low on-resistance (RDSon) that allows the FET switch to exhibit lower voltage drop when current flows through it. This results in the circuit having much higher efficiency in comparison to when a diode is used. For example, if the average current in the system is 5A, the power loss in the diode would be 0.5V x 5A = 2.5 watts (this assumes a Schottky diode with a forward voltage of 0.5V at 5A), versus 5A x 5A x 0.011Ω = 0.275 watts with a transistor having 11 mohm of on-resistance. The transistor achieves better than a 9x reduction in power dissipation. However, with switch-2 integrated onto the die, the S2 losses will be on the die. This will require better thermal design of the die, but the overall improvement in efficiency will result in less total heat generated. The die will require more silicon area when switch S2 and its drive circuitry are included, but this will reduce the board area and component count since the external diode is no longer required.

EEOL 2016JUN13 TA 01Fig3Figure 3: Synchronous buck implementation.

There is another benefit to the synchronous circuit over the asynchronous one that is not obvious to many engineers. When the output load is very low, the inductor current may become discontinuous, meaning the current falls to zero. In the asynchronous configuration, the discontinuous current can result in electromagnetic interference (EMI) emissions. A minimum load may be required for the asynchronous circuit to prevent discontinuous current operation. The synchronous configuration can be designed to enable switch S2 to be turned on under light load conditions. This will allow negative inductor current to flow. While this decreases efficiency at light loads, it allows continuous current flow and prevents EMI. Therefore, the buck regulator, implemented as a synchronous buck, can provide higher efficiency and lower EMI while occupying less board space than the asynchronous version using a diode. The synchronous buck provides even more benefits if its implementation is optimised for the specific voltage regulation applications. A circuit implementation of the synchronous buck would use FET transistors for the upper and lower switches. The lower FET is always an N-channel FET. N-channel devices offer higher electron mobility, and therefore lower resistance for a given size. Nevertheless, the upper FET In a synchronous buck converter can be implemented as either an N-channel or a P-channel. Each has its own advantages and disadvantages.
N-channel vs. P-channel high-side FET switch
Now we'll examine why it can be better to employ buck regulators that use a P-channel device as the upper FET in some applications. But first, let's take a look at the switching section of a synchronous converter with an upper N-channel FET as shown in figure 4.

EEOL 2016JUN13 TA 01Fig4Figure 4: Synchronous buck with N-channel high-side FET switch.

When an N-channel FET is used for the upper switch, there must be a voltage supply source greater than the voltage supplying the drain of the upper switch. For the N-channel FET to turn on with its source voltage at Vs, its gate voltage must be several volts higher than Vs. This higher voltage is typically generated by using a boot capacitor. When the lower FET is on and the upper FET is off, the boot capacitor is charged by the Vc supply. Note that Vs and Vc may be equal or different in the buck converter that uses an N-channel FET for the upper switch. If Vs is higher than Vc, the IC will need to include a level shifter to level shift the PWM signal up to the drive stage that operates at the higher Vc and boot voltage level. When the lower FET turns off and upper FET turns on, the bottom side of the boot capacitor increases to the Vs voltage on the inductor's input. When this occurs, the top side of the boot capacitor has an approximate voltage of Vs + Vc relative to ground. The upper FET's gate and the voltage swing on the boot capacitor's top side both swing from ground at their lowest potential to Vs + Vc when the upper FET is switched on.

EEOL 2016JUN13 TA 01Tab1 Table 1: Upper high-side FET N-channel.

Let's now compare this to the synchronous buck converter that uses a P-channel FET as the upper switch. This arrangement is shown in figure 5. In this circuit, the gate of the upper FET needs only to switch between ground when the upper FET is on, and Vc when the upper FET is off. There is no need for a boot capacitor and the entire circuit can operate at the Vc supply voltage potential.

EEOL 2016JUN13 TA 01Fig5Figure 5: Synchronous Buck with P-channel high-side FET switch.

EEOL 2016JUN13 TA 01Tab2*Table 2: Upper high-side P-Channel-FET. *
Making the right choice
The ISL78233, ISL78234 and ISL78235 pin compatible devices use the P-channel configuration. They integrate a low on-resistance P-channel (35mΩ, typical) high-side FET and N-Channel (11mΩ, typical) low-side FET to maximise efficiency. At 100% duty cycle operation, there is less than 250mV drop across the P-Channel FET at 5A output current. Most of the time, the devices will be converting 5V down to a voltage as low as 0.6V, and the duty ratio will be below 50%. Therefore, even though the P-channel FET has higher resistance than the N-channel FET, the P-channel will be switched on for much less time, and will have less impact on efficiency.

EEOL 2016JUN13 TA 01Fig6 Figure 6: Typical application for ISL78235 5A sync buck regulator.

The ISL7823x devices shown in figure 6 are designed to operate from lower input voltages (+5.5 V down to 2.7 V). As a result, most of their transistors use a smaller geometry, take up less die area and can switch at higher speeds. And since the gate of the upper P-channel FET is driven with the same supply, the signal swing is lower than if an N-channel arrangement is used. This also enables faster switching. The devices can operate with a clock as high as 4MHz, and when set to switch at 2MHz, they can achieve a guaranteed minimum on time of only 100ns. Since 2MHz has a period of 500ns, the devices can down convert with a guaranteed 20% minimum duty ratio. This enables the regulators to output a wide range of voltages while operating at a high frequency. A 100% duty ratio is possible because no time is required to charge a boot capacitor (the ISL7823x devices do not use one). Moreover, no boot capacitor equates to no radiated fields. The high 2MHz switching frequency also enables the use of a smaller power inductor and lower valued capacitors on the regulator's input and output. It's also above the AM radio band and helps prevent EMI at these frequencies.
Wettable flank QFN package
All three of the ISL7823x devices are available in 5mm x 5mm 16-lead wettable flank thin quad flat no-lead (WFQFN) packages with an exposed pad for improved thermal performance. Because they offer 3A, 4A or 5A output current options, it's easy to upgrade a design just by dropping in a new IC with no change in the PCB layout. This saves development costs and time! In addition, the wettable flank package enhances verification of automotive manufacturing quality as it enables optical inspection to verify proper soldering joints as shown in figure 7.

EEOL 2016JUN13 TA 01Fig7 * Figure 7: Visual close up of ISL78235 wettable flank QFN package with reliable solder joints.*

Today's growth in sophisticated cockpit electronics is requiring higher current power supply regulation at lower voltages. POL power supplies need buck regulators that generate very low voltages for GPUs and other higher current devices powered from a primary supply rail of 5V or 3.3V. System designers want to save design time by using the same POL devices across their entire vehicle line up from entry-level to luxury car models. To achieve these goals, we've shown that synchronous buck regulators that use high-side P-channel MOSFETs and other architectural enhancements deliver the optimised secondary power rail solution demanded by power supply designers. With auto manufacturers driving for higher levels of innovation, they look to their semiconductor suppliers to deliver the flexible, rugged and higher performance ICs that can help them realise their system design goals.
About the author
Jerome Johnston is an Applications Engineer with Intersil Corporation's Central Applications team. He has more than 30 years of analogue system design and applications experience, and is the recipient of 13 U.S. patents. Jerome received his BSEE from the University of Nebraska.