Primary-side regulated (PSR) flyback converters (figure 1) have been a popular choice for reducing standby power in low-power adapters and bias supplies. These controllers have been able to achieve less than 5 mW of no-load standby power by using a frequency modulation (FM), current amplitude modulation (AM) scheme to reduce switching losses and standby power. A significant problem with this control scheme is that the converter has slow transient response at light loads, which the designer has to overcome by adding more output capacitance to meet hold-up requirements. The technique described will enable PSR flyback designers to design for higher power densities and reduce overall design cost.

Figure 1: Schematic of an offline primary-side regulated flyback converter.

Before discussing how to speed up the PSR flyback converter, let us review the PSR flyback control methodology. The PSR control scheme senses at the VS pin the scaled output voltage (V OUT) through the transformer's auxiliary-turns ratio (N A/NS). This technique eliminates the need for TL431 opto-isolator feedback circuitry. Removing this circuitry reduces your design's standby power by roughly 2.5 to 5 mW. Equation 1 describes the mathematical relationship between VS and V OUT.

PSR controllers use a combination of valley switching, FM and primary peak current (I PP) amplitude modulation to control the duty cycle (D) of a quasi-resonant / discontinuous flyback converter. Equation 2 is a simplified equation describing the D of this offline power converter. Variable t ON is the switch (Q1) on time. Variable tC is the time when the output diode (D G) is conducting and the transformer (T1) is delivering energy to the output of the converter. Variable t D is the dead time adjusted by the PSR controller to then adjust the duty cycle.

The traditional PSR controller feedback circuitry will only sample the voltage on the auxiliary winding (V A) when the transformer is delivering energy to the secondary (during t C). The circuitry will generally take this sample just before the output diode stops conducting current (I DG). After taking the sample, the controller will adjust both IPP and the converter's dead time to set the duty cycle for the switching period (figure 2). These PSR controllers typically operate at switching frequencies from 100kHz (f MAX) at full load down to a minimum switching frequency of 1kHz (f MIN) when the power converter is idle.

When the power converter is idle, it could take up to 1 ms for the output to respond to sudden load changes. This puts a large amount of stress on the output capacitor to hold up the output voltage during worse-case transients. The output capacitance (C OUT1) needs to be selected based on the maximum current load step (I MAX), the minimum switching frequency (f MIN) and the maximum allowable voltage droop (dV) (Equation 3).

Figure 2: PSR feedback sampling and duty-cycle control.

A technique known as wake-up monitoring with PSR sampling initiation speeds up transient response using the auxiliary to secondary turns ratio (N A/NS). This control scheme, which retains all of the functions of a traditional PSR flyback controller, requires a PSR controller ( UCC28730) and a secondary wake-up monitor ( UCC24650) that work together. This control scheme uses a PSR with all the functions of a traditional PSR flyback controller. However, the device has a function that when activated initiates output sampling to begin IPP, frequency and duty-cycle adjustment.

Activating this function requires a positive pulse at the controller's VS pin during the converter's dead time after the auxiliary winding stops ringing. The wake-up monitor will sample and store the output voltage (V OUT1) when the transformer is delivering energy from the primary to the secondary.

During the converter's dead time, the wake-up chip will continue to monitor the output voltage (V OUT2). If V OUT2 drops to 97 per cent of V OUT1, the wake-up chip will short the secondary winding of the flyback transformer with a current-limited switch for 1µs once every 30µs. This will generate a positive pulse or pulses on the auxiliary winding of the transformer, alerting the PSR that there is a low-output voltage condition and that the controller needs to sample the output and respond accordingly (figure 3).

Figure 3: Wake-up monitoring with PSR sample initiation.

The output capacitance (C OUT2) for a PSR flyback with wake-up monitoring has to be sized for hold-up and is also used for loop stability. The capacitor is generally sized for one-tenth the maximum switching frequency, which is less capacitance than in traditional PSR flyback converters. This output capacitance can be calculated with Equation 4.

To show how much the output capacitance can be reduced, let's generate an equation (Equation 5) from the calculations for C OUT1 and C OUT2. The equation for C OUT1 was solved in terms of I MAX and then substituted into the equation for calculating the output capacitance (C OUT2) of a PSR flyback converter with a wake-up technique. For a design where the minimum switching (f MIN) was set to 1kHz and the maximum switching (f MAX) was designed for 65kHz, the output capacitance required by this new wake-up control scheme would be 6.5 times smaller than the output capacitance (C OUT1) used in a traditional PSR flyback converter. The amount of reduction will vary based on f MIN and f MAX.

To show how the wake-up monitor could speed up transient response, I evaluated a 10-W/5-V USB adapter. This converter was designed to operate with a maximum switching (f MAX) of 50kHz. Pre-loading the converter enables the output to maintain regulation with an idle switching frequency (f MIN) of 1.25kHz. The output capacitance for this design was 660µF.

First, I evaluated the adapter with a traditional PSR controller. Then I tested the prototype with 0- to 2-A load (I OUT) transients; the output (V OUT) dropped 3V and out of regulation. The controller used in this application had to wait (t WAIT) 600µs after the load transient for the next output sample (t S) to adjust the duty cycle and respond to the transients. In this application, t WAIT could be as long as 800µs due to PSR feedback sampling and control. See figure 4 for circuit performance.