TI's zero-drift technology achieves a low maximum offset voltage of 5μV and a typical offset voltage drift of 0.005μV/°C.
The group expects to create common configuration files for plug-and-play interoperability to ensure compatibility between each company’s products.
The solution addresses SiC IPMs in hermetically sealed packages currently in development for harsh environments.
The LTC3871 provides bidirectional DC/DC control and battery charging between the 12V and 48V boardnets.
These MOSFETs represent low-current supplements to Toshiba’s existing DTMOS IV line-up of 800V superjunction DTMOS IV devices.
The decision will be accompanied by a shift in the focus of Renesas’ compound semiconductor device business to optical devices.
The LTC6433-15 simplifies wideband design and allows easy cascading with minimal external components.
For applications requiring higher current, up to four units can be connected in parallel to supply up to 320A as a single power rail.
A low-power circuit design secures a nearly 46% current reduction and peak current consumption of 3.6mA at 3V supply voltage in transmitting mode.
It utilises a fixed 2MHz switching frequency, enabling designers to minimise external component sizes and avoid critical frequency bands.