Home | Login | Register Now   [Feb 10,2010]
Global Sources
EE Times-Asia
For Registered Users Home / For Registered Users

Techniques for evaluating deterministic jitter
Author: Sharon Wang, John Abcarius

This article discusses the effects of power supply noise interference on PLL-based clock generators and describes measurement techniques for evaluating the resulting deterministic jitter.

Please login or register with us to view this article>>


If you have already registered on the following websites, please log in using your email address and password

EE Times-Asia sites:

Latest News
Talkback

eeForum:
Demystifying Vietnam

What does Vietnam offer that a rising number of top-tier semiconductor companies are setting up and expanding operations there?

more

 
Top tech resources
 
India Newsletter
 
Go to top