Custom PCI timing budgets for Spartan-3 Generation FPGAs
Author: Xilinx

The PCI Local Bus Specification, Revision 3.0 (the PCI specification), defines two timing budgets. One timing budget is for use with 33MHz operation, and the other timing budget is for use with 66MHz operation. These two timing budgets define the I/O timing parameters for compliant 33MHz and 66MHz components.

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