Interfacing FPGAs to DDR3 SDRAM
Author: Paul Evans

Double-data-rate three (DDR3) SDRAM memory architectures support higher bandwidths with bus rates of 600Mbit/s to 1.6Gbit/s (300- to 800MHz), 1.5V operation for lower power, and higher densities of 2Gbits on a 90nm process. This faster, larger, and lower power per bit architecture is made possible by leveling the interface between a DDR3 SDRAM DIMM to an FPGA.