Valuing substrate parasitics in RFIC designs
Author: Jih-Hsin Liu, Chih-Hao Liao, Ray Lin, Venkat Ramasubramanian, Carl Yang, Bob Mullen

Often, there is a need to simulate RFIC designs with substrate parasitics to accurately represent high-frequency effects in actual silicon. Generally, parasitics appear from a chip's surface layers, especially from metallization routing and coupling, or from the RC parasitics of the silicon substrate.