Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Address SoC routing congestion with 2.5D SiP

Posted: 05 Jun 2014     Print Version  Bookmark and Share

Keywords:embedded systems  System on Chip  SoC  System in Package  SiP 

[Summary of tips] Not very long ago, embedded systems were made up of logic spread across multiple chips—for example, the CPU sub-system. Memory, the analogue components, and so on, were each on their own IC. The advantage was that each chip could be independently designed at its appropriate process technology node (90nm, 130nm, etc.). How......
Please login or register with us to view this article>>
1 • 2 • 3 Next Page Last Page

Article Comments - Address SoC routing congestion with ...
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top