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TSMC fleshes out IC line-up with shrunk TSVs

Posted: 25 Apr 2014     Print Version  Bookmark and Share

Keywords:TSMC  20nm  16nm  FinFET 

[Summary of tips] eda 2 asic Consulting's Herb Reiter relates TSMC's technology roadmap it presented during a symposium in San Jose. The foundry developed low cost packaging technologies as alternatives to its existing Chip on Wafer on Substrate (CoWoS) positioned as a high-end process. The offerings include 28nm, 20nm, 16nm, and the planned 10n......
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