Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Identifying false paths

Posted: 07 Apr 2014     Print Version  Bookmark and Share

Keywords:FPGA  ASIC  timing  synthesis  place-and-route 

[Summary of tips] If only FPGA and/or ASIC designs would meet timing requirements the first time around, life would be simpler for a lot of engineers. Unfortunately, it is not as simple as that. The time and effort spent on timing are reaching unparalleled levels. Designers resort to constraining their synthesis and place-and-route (P&R) tools t......
Please login or register with us to view this article>>
1 • 2 • 3 Next Page Last Page

Article Comments - Identifying false paths
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top