Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Intro to C-slow retiming, system hyper pipelining

Posted: 03 Mar 2014     Print Version  Bookmark and Share

Keywords:pipelining  C-slow retiming  CPU  RTL  verification 

[Summary of tips] I guess everybody knows what pipelining is, and that CPUs are pipelined to optimise their throughput. And we can all agree that inserting registers at the right places in the data path can improve throughput. It's certainly not a unique idea, and this technique is already used in various designs. Having said this, I think this ......
Please login or register with us to view this article>>
1 • 2 • 3 • 4 Next Page Last Page

Article Comments - Intro to C-slow retiming, system hyp...
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top