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Imec, Cadence team up for DFT solution for 3D memory
Keywords:test logic-memory interconnects DRAM-on-logic stacks Wide-I/O mobile design-for-test ATPG approach
[Summary of tips] Nano-electronics research institute imec, has recently announced that it has teamed up with Cadence Design Systems to develop, implement and validate an automated 3D Design-for-Test (DFT) solution to test logic-memory interconnects in DRAM-on-logic stacks. Based on Cadence Encounter technology, the solution was verified on an i......Please login or register with us to view this article>>
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