Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Apply formal methods to power-aware verification

Posted: 02 Jan 2013     Print Version  Bookmark and Share

Keywords:RTL  Unified Power Format  design-for-test 

[Summary of tips] The imperative for minimising power consumption now permeates application spaces ranging from mobile appliances with limited battery life to big-box electronics that consume large amounts of increasingly expensive power. Consequently, power reduction and management methods are now used extensively throughout the chip design flo......
Please login or register with us to view this article>>
1 • 2 Next Page Last Page

Article Comments - Apply formal methods to power-aware ...
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top