EDA/IP 
Cadence synthesis tech eases Renesas ASIC design
Keywords:ASIC design Renesas Encounter RTL Compiler place-and-route cycles
[Summary of tips] Cadence Design Systems Inc. has revealed that Renesas Micro Systems Co. Ltd has adopted the Cadence Encounter RTL Compiler for synthesis. According to the company, it claims to improve utilisation by 15 per cent, area reduction by 8.4 per cent, quick turnaround time and cost reduction for complex ASIC designs."Renesas Micro Sys......Please login or register with us to view this article>>
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