EDA/IP 
Tools offer shared database for design, verification
Keywords: chip design formal verification RTL
[Summary of tips] From Jasper Design Automation Inc. come improved versions of the ActiveDesign and JasperGold tools with capabilities that bridge the divide between chip design and verification by sharing a common, persistent knowledge base.Jasper's ActiveDesign with behavioral indexing lets users design, concurrently modify and verify their RT......Please login or register with us to view this article>>
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