EDA/IP 
Scaling custom digital layout for next-generation chip design
Keywords: chip design custom digital layout 40nm semiconductor
[Summary of tips] Layout for large digital IC designs is generally created using highly automated place-and-route (APR) tools. Although there are trade-offs for using APR instead of custom layout, the speed and confidence offered by APR far out weigh the compromises in area or performance for most designs. But designs that require the utmost in ......Please login or register with us to view this article>>
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