Global Sources
EE Times-Asia
Advanced Search
News
Products
Technical Articles
App Notes
ForumBlogsWhite PapersDatasheetsWebinars
 Challenges & Opportunities 2011     MCU     MEMS     IGBT     processor     LED     RFID
EE Times-Asia > EDA/IP
 
 
EDA/IP  

Synthesis tool handles complex design verification

Posted: 11 May 2010  Print Version  Bookmark and Share Subscribe

Keywords: SoC design  verification  synthesis tool  EDA 

[Summary of tips] EDA startup NextOp Software Inc. is bridging design and verification with the introduction of what it claims is the first assertion-based verification solution to automatically generate high quality assertions and functional coverage properties from testbench and RTL.The company's initial product, dubbed BugScope, is a full-chi......
Please login or register with us to view this article>>
1 • 2 Next Page Last Page
 

votes:   Add to Favorites
ESD physical integrity tool enables ...
Software tool eases timing solution ...
Article Comments - Synthesis tool handles complex desig...
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
Top Ranked Articles
High-quality Articles
Christmas Wishlist
    Kindle Fire Hot CE innovations at the CES

    All I want for Christmas is any of this year's Best of Innovations Design and Engineering Award honorees! Here's the EE Times pick for Top 10 CE gadgets.

Search EE Times Asia
Peek at Hot Gadgets for 2012
Smart energy "Try explaining to your eight-year-old son that instead of an Xbox, you got him a Wi-Fi enabled smart energy thermostat to help minimize his energy consumption and carbon footprint..."
 

Go to top