Embedded 
Processor packs L2 cache for improved performance
Keywords: processor L2 cache FPGA
[Summary of tips] eASIC Corp. has released the Aeroflex Gaisler's LEON4 processor, as part of its eZ-IP Alliance Core Library. LEON4 is a high-performance, 32bit processor core based on the SPARC V8 architecture. The new LEON4 core complements the LEON3 processor for high-performance embedded applications across a broad spectrum of demanding con......Please login or register with us to view this article>>
|
Not yet registered?
 Register FREE to view unlimited features, tutorials and products, and enable any content alert service! |
Registered already? Login to view complete content.
|
| Related Articles | Editor's Choice |
Article Comments - Processor packs L2 cache for improve...
Visitor0211
(To avoid code verification, simply login or register with us. It is fast and free!)
Top Ranked Articles
Christmas Wishlist
All I want for Christmas is anything on this year's Best of Innovations Design and Engineering Award list!
Search EE Times Asia
Peek at Hot Gadgets for 2012
