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EDA/IP  

IP core supports Serial RapidIO 2.1

Posted: 20 Nov 2009  Print Version  Bookmark and Share Subscribe

Keywords: IP core  RapidIO 2.1  interface  DSP 

[Summary of tips] Altera Corp. unleashes what it claims to be the first IP core to support the RapidIO 2.1 specification. The IP core supports up to four lanes at 5GBaud per lane, addressing the increased bandwidth and reliability needs of the wireless and military markets. It is optimized for Stratix IV FPGAs with embedded transceivers and is s......
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