EDA/IP 
Yield tool minimizes design re-spin
Keywords:management tool yield re spin design test
[Summary of tips] At the IEEE International Symposium on Quality Electronic Design (ISQED) conference, Synopsys Inc. introduced Yield Explorer, a new yield management tool that expedites the discovery and mitigation of yield limiters in leading-edge ICs.Yield Explorer minimizes design re-spin through rapid and comprehensive capture of design-pro......Please login or register with us to view this article>>
|
Not yet registered?
 Register FREE to view unlimited features, tutorials and products, and enable any content alert service! |
Registered already? Login to view complete content.
|
Article Comments - Yield tool minimizes design re-spin
Visitor(To avoid code verification, simply login or register with us. It is fast and free!)
Top Ranked Articles
Christmas Wishlist
All I want for Christmas is anything on this year's Best of Innovations Design and Engineering Award list!
Search EE Times Asia
