EDA/IP 
The bad stuff impacting DDR timing budgets and ways to avoid 'em
Keywords: blog DDR PHY SSTL PLL DLL
[Summary of tips] By Navraj Nandra The Eyes Have ItThe color coded schemeJust returned from Asia and one of the questions often asked on this trip was: why bother with a DDR "PHY" when some SSTL I/O's with potentially a DLL or PLL slapped together with glue logic will do the trick of interfacing to an SDRAM? Oh, not forgetting the RTL for the ac......Please login or register with us to view this article>>
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