Interface 
Interfacing the MAX5881 direct RF synthesis DAC to FPGAs
Keywords: interfacing techniques MAX5881 FPGA high-speed interface data
[Summary of tips] This application note discusses techniques for interfacing the MAX5881, a 4.3GSps cable downstream direct RF synthesis DAC, to FPGAs. The focus is on the timing of the MAX5881's high-speed, digital input data interface to a Xilinx Virtex-5 FPGA. However, the techniques outlined here are also applicable to a wide variety of FPGA......Please login or register with us to view this article>>
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