Embedded 
XPLA3 I/O cell characteristics
Keywords: XPLA3 I/O cell EMI XPLA CPLDs impedance
[Summary of tips] The I/O cell architecture used in XPLA3 CPLDs is intended to give designers maximum control and flexibility when implementing their designs. Each I/O cell can be implemented in one of several different modes such as a high impedance input, input with weak pull-up, output, bidirectional, or unused pin without the need for extern......Please login or register with us to view this article>>
|
Not yet registered?
 Register FREE to view unlimited features, tutorials and products, and enable any content alert service! |
Registered already? Login to view complete content.
|
Article Comments - XPLA3 I/O cell characteristics
Visitor0213
(To avoid code verification, simply login or register with us. It is fast and free!)
Top Ranked Articles
Christmas Wishlist
All I want for Christmas is anything on this year's Best of Innovations Design and Engineering Award list!
Search EE Times Asia
Peek at Hot Gadgets for 2012
