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Perform low-power manufacturing test

Posted: 16 Jan 2008  Print Version  Bookmark and Share Subscribe

Keywords: design-for-test process  DFT process  scan ATPG algorithms  low-power manufacturing tests  dynamic power consumption 

[Summary of tips] The very process of testing digital circuits routinely increases their dynamic power consumption to levels exceeding their power specification. If the power consumption is great enough, it can result in failures at wafer probe or pre-burn-in package test that require a significant amount of time and effort to debug. This issue,......
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