Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > T&M

EDA's big three unready for 3D chip packaging

Posted: 25 Oct 2007     Print Version  Bookmark and Share

Keywords:EDA  3D layout  chip packaging 

[Summary of tips] IMEC is putting a renewed emphasis on chip packaging—and on 3D-integration in particular—according to plans revealed at a press briefing before last week's Annual Research Review Meeting. However, IMEC and European chip company experts are not expecting much help to come from the "big three" EDA companies—usua......
Please login or register with us to view this article>>

Article Comments - EDA's big three unready for 3D chip ...
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top